Commit 111b2959 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:

 - Fix kexec and hibernation when using 5-level page-table configuration

 - Remove references to non-existent SF8MM4 and SF8MM8 ID register
   fields, hooking up hwcaps for the FPRCVT, F8MM4 and F8MM8 fields
   instead

 - Drop unused .ARM.attributes ELF sections

 - Fix array indexing when probing CPU cache topology from firmware

 - Fix potential use-after-free in AMU initialisation code

 - Work around broken GTDT entries by tolerating excessively large timer
   arrays

 - Force use of Rust's "softfloat" target to avoid a threatening warning
   about the NEON target feature

 - Typo fix in GCS documentation and removal of duplicate Kconfig select

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: rust: clean Rust 1.85.0 warning using softfloat target
  arm64: Add missing registrations of hwcaps
  ACPI: GTDT: Relax sanity checking on Platform Timers array count
  arm64: amu: Delay allocating cpumask for AMU FIE support
  arm64: cacheinfo: Avoid out-of-bounds write to cacheinfo array
  arm64: Handle .ARM.attributes section in linker scripts
  arm64/hwcap: Remove stray references to SF8MMx
  arm64/gcs: Fix documentation for HWCAP
  arm64: Kconfig: Remove selecting replaced HAVE_FUNCTION_GRAPH_RETVAL
  arm64: Fix 5-level paging support in kexec/hibernate trampoline
parents 93bd481b 446a8351

Documentation/arch/arm64/gcs.rst

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ intended to be exhaustive. 
  shadow stacks rather than GCS.



* Support for GCS is reported to userspace via HWCAP_GCS in the aux vector

  AT_HWCAP2 entry.

  AT_HWCAP entry.



* GCS is enabled per thread.  While there is support for disabling GCS

  at runtime this should be done with great care.

arch/arm64/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -225,7 +225,6 @@ config ARM64 
	select HAVE_FUNCTION_ERROR_INJECTION

	select HAVE_FUNCTION_GRAPH_FREGS

	select HAVE_FUNCTION_GRAPH_TRACER

	select HAVE_FUNCTION_GRAPH_RETVAL

	select HAVE_GCC_PLUGINS

	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \

		HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI

arch/arm64/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -48,7 +48,11 @@ KBUILD_CFLAGS += $(CC_FLAGS_NO_FPU) \ 
KBUILD_CFLAGS	+= $(call cc-disable-warning, psabi)

KBUILD_AFLAGS	+= $(compat_vdso)



ifeq ($(call test-ge, $(CONFIG_RUSTC_VERSION), 108500),y)

KBUILD_RUSTFLAGS += --target=aarch64-unknown-none-softfloat

else

KBUILD_RUSTFLAGS += --target=aarch64-unknown-none -Ctarget-feature="-neon"

endif



KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)

KBUILD_AFLAGS	+= $(call cc-option,-mabi=lp64)

arch/arm64/kernel/cacheinfo.c

+7 −5
Original line number Diff line number Diff line
@@ -101,16 +101,18 @@ int populate_cache_leaves(unsigned int cpu) 
	unsigned int level, idx;

	enum cache_type type;

	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct cacheinfo *this_leaf = this_cpu_ci->info_list;

	struct cacheinfo *infos = this_cpu_ci->info_list;



	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&

	     idx < this_cpu_ci->num_leaves; idx++, level++) {

	     idx < this_cpu_ci->num_leaves; level++) {

		type = get_cache_type(level);

		if (type == CACHE_TYPE_SEPARATE) {

			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);

			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);

			if (idx + 1 >= this_cpu_ci->num_leaves)

				break;

			ci_leaf_init(&infos[idx++], CACHE_TYPE_DATA, level);

			ci_leaf_init(&infos[idx++], CACHE_TYPE_INST, level);

		} else {

			ci_leaf_init(this_leaf++, type, level);

			ci_leaf_init(&infos[idx++], type, level);

		}

	}

	return 0;

arch/arm64/kernel/cpufeature.c

+3 −2
Original line number Diff line number Diff line
@@ -3091,6 +3091,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),

	HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),

	HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),

	HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT),

	HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),

	HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),

	HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
@@ -3180,8 +3181,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM8),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM4),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM),

	HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES),

	HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA),
@@ -3192,6 +3191,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),

	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),

#ifdef CONFIG_ARM64_POE