Commit 111fdd21 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: drm_gpuvm conversion 



Now that we've realigned deletion and allocation, switch over to using
drm_gpuvm/drm_gpuva.  This allows us to support multiple VMAs per BO per
VM, to allow mapping different parts of a single BO at different virtual
addresses, which is a key requirement for sparse/VM_BIND.

This prepares us for using drm_gpuvm to translate a batch of MAP/
MAP_NULL/UNMAP operations from userspace into a sequence of map/remap/
unmap steps for updating the page tables.

Since, unlike our prior vm/vma setup, with drm_gpuvm the vm_bo holds a
reference to the GEM object.  To prevent reference loops causing us to
leak all GEM objects, we implicitly tear down the mapping when the GEM
handle is close or when the obj is unpinned.  Which means the submit
needs to also hold a reference to the vm_bo, to prevent the VMA from
being torn down while the submit is in-flight.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Tested-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Reviewed-by: default avatarAntonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/661479/
parent 8ac37c88

drivers/gpu/drm/msm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ config DRM_MSM 
	select DRM_DISPLAY_HELPER

	select DRM_BRIDGE_CONNECTOR

	select DRM_EXEC

	select DRM_GPUVM

	select DRM_KMS_HELPER

	select DRM_PANEL

	select DRM_BRIDGE

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+1 −2
Original line number Diff line number Diff line
@@ -472,8 +472,7 @@ a2xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev) 
	struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);

	struct msm_gem_vm *vm;



	vm = msm_gem_vm_create(mmu, "gpu", SZ_16M,

		0xfff * SZ_64K);

	vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", SZ_16M, 0xfff * SZ_64K, true);



	if (IS_ERR(vm) && !IS_ERR(mmu))

		mmu->funcs->destroy(mmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+3 −3
Original line number Diff line number Diff line
@@ -1311,7 +1311,7 @@ static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 
	return 0;

}



static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)

static int a6xx_gmu_memory_probe(struct drm_device *drm, struct a6xx_gmu *gmu)

{

	struct msm_mmu *mmu;
@@ -1321,7 +1321,7 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 
	if (IS_ERR(mmu))

		return PTR_ERR(mmu);



	gmu->vm = msm_gem_vm_create(mmu, "gmu", 0x0, 0x80000000);

	gmu->vm = msm_gem_vm_create(drm, mmu, "gmu", 0x0, 0x80000000, true);

	if (IS_ERR(gmu->vm))

		return PTR_ERR(gmu->vm);
@@ -1940,7 +1940,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
	if (ret)

		goto err_put_device;



	ret = a6xx_gmu_memory_probe(gmu);

	ret = a6xx_gmu_memory_probe(adreno_gpu->base.dev, gmu);

	if (ret)

		goto err_put_device;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −3
Original line number Diff line number Diff line
@@ -2284,9 +2284,8 @@ a6xx_create_private_vm(struct msm_gpu *gpu) 
	if (IS_ERR(mmu))

		return ERR_CAST(mmu);



	return msm_gem_vm_create(mmu,

		"gpu", ADRENO_VM_START,

		adreno_private_vm_size(gpu));

	return msm_gem_vm_create(gpu->dev, mmu, "gpu", ADRENO_VM_START,

				 adreno_private_vm_size(gpu), true);

}



static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+4 −3
Original line number Diff line number Diff line
@@ -226,7 +226,8 @@ adreno_iommu_create_vm(struct msm_gpu *gpu, 
	start = max_t(u64, SZ_16M, geometry->aperture_start);

	size = geometry->aperture_end - start + 1;



	vm = msm_gem_vm_create(mmu, "gpu", start & GENMASK_ULL(48, 0), size);

	vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", start & GENMASK_ULL(48, 0),

			       size, true);



	if (IS_ERR(vm) && !IS_ERR(mmu))

		mmu->funcs->destroy(mmu);
@@ -414,12 +415,12 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, 
	case MSM_PARAM_VA_START:

		if (ctx->vm == gpu->vm)

			return UERR(EINVAL, drm, "requires per-process pgtables");

		*value = ctx->vm->va_start;

		*value = ctx->vm->base.mm_start;

		return 0;

	case MSM_PARAM_VA_SIZE:

		if (ctx->vm == gpu->vm)

			return UERR(EINVAL, drm, "requires per-process pgtables");

		*value = ctx->vm->va_size;

		*value = ctx->vm->base.mm_range;

		return 0;

	case MSM_PARAM_HIGHEST_BANK_BIT:

		*value = adreno_gpu->ubwc_config.highest_bank_bit;