Commit 114a89b4 authored by Alison Schofield's avatar Alison Schofield Committed by Dave Jiang
Browse files

cxl/test: Define a CFMWS capable of a 3 way HB interleave 



The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
interleave test case because the window is not defined.

Additionally, upcoming expansion of 3 way HB interleave test cases
(like 2+2+2) require the same window.

Replace an unused CFMWS with a 3-way capable CFMWS in the set of
CFMWS's loaded when interleave_arithmetic=1.

Signed-off-by: default avatarAlison Schofield <alison.schofield@intel.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Tested-by: default avatarLi Zhijian <lizhijian@fujitsu.com>
Link: https://patch.msgid.link/20250226221931.2352061-1-alison.schofield@intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 84f8b6e2

tools/testing/cxl/test/cxl.c

+5 −5
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ static struct { 
	} cfmws7;

	struct {

		struct acpi_cedt_cfmws cfmws;

		u32 target[4];

		u32 target[3];

	} cfmws8;

	struct {

		struct acpi_cedt_cxims cxims;
@@ -331,14 +331,14 @@ static struct { 
				.length = sizeof(mock_cedt.cfmws8),

			},

			.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,

			.interleave_ways = 2,

			.granularity = 0,

			.interleave_ways = 8,

			.granularity = 1,

			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |

					ACPI_CEDT_CFMWS_RESTRICT_PMEM,

			.qtg_id = FAKE_QTG_ID,

			.window_size = SZ_256M * 16UL,

			.window_size = SZ_512M * 6UL,

		},

		.target = { 0, 1, 0, 1, },

		.target = { 0, 1, 2, },

	},

	.cxims0 = {

		.cxims = {