Commit 118a3315 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN3.1 clock manager support 



Adds support for clock requests for the various parts of the DCN3.1 IP
and the interfaces and definitions for sending messages to SMU/PMFW.

Includes new support for z9/10, detecting SMU timeout and p-state
support enablement.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d997ea5c

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+6 −0
Original line number Diff line number Diff line
@@ -655,6 +655,12 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 
	/* TODO: something */

}



void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)

{

	// TODO:

	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);

}



void *dm_helpers_allocate_gpu_mem(

		struct dc_context *ctx,

		enum dc_gpu_mem_alloc_type type,

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+11 −0
Original line number Diff line number Diff line
@@ -136,3 +136,14 @@ AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_ 


AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)

endif



ifdef CONFIG_DRM_AMD_DC_DCN3_1

###############################################################################

# DCN31

###############################################################################

CLK_MGR_DCN31 = dcn31_smu.o dcn31_clk_mgr.o



AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DCN31))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)

endif

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+30 −0
Original line number Diff line number Diff line
@@ -41,6 +41,9 @@ 
#include "dcn21/rn_clk_mgr.h"

#include "dcn30/dcn30_clk_mgr.h"

#include "dcn301/vg_clk_mgr.h"

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

#include "dcn31/dcn31_clk_mgr.h"

#endif





int clk_mgr_helper_get_active_display_cnt(
@@ -261,6 +264,26 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
		}

		break;

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case FAMILY_YELLOW_CARP: {

		struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);



		if (clk_mgr == NULL) {

			BREAK_TO_DEBUGGER();

			return NULL;

		}

		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) {

			/* TODO: to add DCN31 clk_mgr support, once CLK IP header files are available,

			 * for now use DCN3.0 clk mgr.

			 */

			dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			return &clk_mgr->base.base;

		}

		return &clk_mgr->base.base;

	}

#endif



	default:

		ASSERT(0); /* Unknown Asic */

		break;
@@ -292,6 +315,13 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) 
			vg_clk_mgr_destroy(clk_mgr);

		break;



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case FAMILY_YELLOW_CARP:

		if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev))

			dcn31_clk_mgr_destroy(clk_mgr);

		break;

#endif



	default:

		break;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+4 −0
Original line number Diff line number Diff line
@@ -324,6 +324,10 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 
	// Both fclk and ref_dppclk run on the same scemi clock.

	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	/* TODO: set dtbclk in correct place */

	clk_mgr->clks.dtbclk_en = false;

#endif

	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

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+673 −0

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