Unverified Commit 11949d26 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt



RISC-V Devicetrees for v6.17

Sophgo:

For CV18xx serials:
There are three major changes. The first is to add the
RTCSYS MFD node, which provides rich control registers
for soc power management and other rich control functions;
the second is to add the reset controller node and add
related reset properties for other peripherals; the third
is to add ethernet controller related nodes to the soc
and enable ethernet device control for HuashanPi.

For SG2042:
There are three major changes. The first is to add ISA
extensions such as xtheadvector/ziccrse/zfh for cpu cores;
the second is add ethernet controller support; the third
is add two new boards EVB_V1 & EVB_V2 which use SG2042
SoC.

For SG2044:
There are many changes. The first is to add pmu
configuration; the second is to add ISA extensions
ziccrse and add missing riscv,cbop-block-size property
for cpu cores; the third is to add more peripherals
nodes for SoC after clock controller is ready, such as
MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU
device for the sophgo-srd3-10 board and reserve uart0
node for sophgo-srd3-10 board because uart0 is already
occupied by the firmware.

This PR also moves sophgo.yaml from the riscv directory
to soc/sophgo for sharing between riscv and arm. CV18xx
SoC contains a RISC-V big core and an ARM64 big core.
Moving sophgo.yaml to a shared location will help us
add support for ARM cores to the CV18xx chip in the future.

Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits)
  riscv: dts: sophgo: fix mdio node name for CV180X
  riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
  dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
  riscv: dts: sophgo: add ethernet GMAC device for sg2042
  riscv: dts: sophgo: Enable ethernet device for Huashan Pi
  riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
  riscv: dts: sophgo: Add ethernet device for cv18xx
  riscv: dts: sophgo: sg2044: add pmu configuration
  riscv: dts: sophgo: sg2044: add ziccrse extension
  riscv: dts: sophgo: add zfh for sg2042
  riscv: dts: sophgo: add ziccrse for sg2042
  riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
  riscv: dts: sophgo: sg2044: add MSI device support for SG2044
  riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
  dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
  riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
  ...

Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents cd7dace0 7f905730
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+8 −1
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo SoC-based boards
@@ -26,6 +26,11 @@ properties:
          - enum:
              - sophgo,huashan-pi
          - const: sophgo,cv1812h
      - items:
          - enum:
              - milkv,duo-module-01-evb
          - const: milkv,duo-module-01
          - const: sophgo,sg2000
      - items:
          - enum:
              - sipeed,licheerv-nano-b
@@ -34,6 +39,8 @@ properties:
      - items:
          - enum:
              - milkv,pioneer
              - sophgo,sg2042-evb-v1
              - sophgo,sg2042-evb-v2
          - const: sophgo,sg2042
      - items:
          - enum:
+2 −0
Original line number Diff line number Diff line
@@ -3,4 +3,6 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
+110 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx-reset.h"

/ {
	#address-cells = <1>;
@@ -24,11 +25,45 @@ soc {
		#size-cells = <1>;
		ranges;

		rst: reset-controller@3003000 {
			compatible = "sophgo,cv1800b-reset";
			reg = <0x3003000 0x1000>;
			#reset-cells = <1>;
		};

		mdio: mdio-mux@3009800 {
			compatible = "mdio-mux-mmioreg", "mdio-mux";
			reg = <0x3009800 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			mdio-parent-bus = <&gmac0_mdio>;
			mux-mask = <0x80>;
			status = "disabled";

			internal_mdio: mdio@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				internal_ephy: phy@0 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <1>;
				};
			};

			external_mdio: mdio@80 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x80>;
			};
		};

		gpio0: gpio@3020000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x3020000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst RST_GPIO0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
@@ -47,6 +82,7 @@ gpio1: gpio@3021000 {
			reg = <0x3021000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst RST_GPIO1>;

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
@@ -65,6 +101,7 @@ gpio2: gpio@3022000 {
			reg = <0x3022000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst RST_GPIO2>;

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
@@ -83,6 +120,7 @@ gpio3: gpio@3023000 {
			reg = <0x3023000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&rst RST_GPIO3>;

			portd: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
@@ -126,6 +164,7 @@ i2c0: i2c@4000000 {
			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
			clock-names = "ref", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_I2C0>;
			status = "disabled";
		};

@@ -137,6 +176,7 @@ i2c1: i2c@4010000 {
			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
			clock-names = "ref", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_I2C1>;
			status = "disabled";
		};

@@ -148,6 +188,7 @@ i2c2: i2c@4020000 {
			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
			clock-names = "ref", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_I2C2>;
			status = "disabled";
		};

@@ -159,6 +200,7 @@ i2c3: i2c@4030000 {
			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
			clock-names = "ref", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_I2C3>;
			status = "disabled";
		};

@@ -170,9 +212,56 @@ i2c4: i2c@4040000 {
			clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
			clock-names = "ref", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_I2C4>;
			status = "disabled";
		};

		gmac0: ethernet@4070000 {
			compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
			reg = <0x04070000 0x10000>;
			clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
			clock-names = "stmmaceth", "ptp_ref";
			interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			phy-handle = <&internal_ephy>;
			phy-mode = "internal";
			resets = <&rst RST_ETH0>;
			reset-names = "stmmaceth";
			rx-fifo-depth = <8192>;
			tx-fifo-depth = <8192>;
			snps,multicast-filter-bins = <0>;
			snps,perfect-filter-entries = <1>;
			snps,aal;
			snps,txpbl = <8>;
			snps,rxpbl = <8>;
			snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
			snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
			snps,axi-config = <&gmac0_stmmac_axi_setup>;
			status = "disabled";

			gmac0_mdio: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
			};

			gmac0_mtl_rx_setup: rx-queues-config {
				snps,rx-queues-to-use = <1>;
				queue0 {};
			};

			gmac0_mtl_tx_setup: tx-queues-config {
				snps,tx-queues-to-use = <1>;
				queue0 {};
			};

			gmac0_stmmac_axi_setup: stmmac-axi-config {
				snps,blen = <16 8 4 0 0 0 0>;
				snps,rd_osr_lmt = <2>;
				snps,wr_osr_lmt = <1>;
			};
		};

		uart0: serial@4140000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x04140000 0x100>;
@@ -181,6 +270,7 @@ uart0: serial@4140000 {
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst RST_UART0>;
			status = "disabled";
		};

@@ -192,6 +282,7 @@ uart1: serial@4150000 {
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst RST_UART1>;
			status = "disabled";
		};

@@ -203,6 +294,7 @@ uart2: serial@4160000 {
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst RST_UART2>;
			status = "disabled";
		};

@@ -214,6 +306,7 @@ uart3: serial@4170000 {
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst RST_UART3>;
			status = "disabled";
		};

@@ -225,6 +318,7 @@ spi0: spi@4180000 {
			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
			clock-names = "ssi_clk", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_SPI0>;
			status = "disabled";
		};

@@ -236,6 +330,7 @@ spi1: spi@4190000 {
			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
			clock-names = "ssi_clk", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_SPI1>;
			status = "disabled";
		};

@@ -247,6 +342,7 @@ spi2: spi@41a0000 {
			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
			clock-names = "ssi_clk", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_SPI2>;
			status = "disabled";
		};

@@ -258,6 +354,7 @@ spi3: spi@41b0000 {
			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
			clock-names = "ssi_clk", "pclk";
			interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rst RST_SPI3>;
			status = "disabled";
		};

@@ -269,6 +366,7 @@ uart4: serial@41c0000 {
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst RST_UART4>;
			status = "disabled";
		};

@@ -307,5 +405,17 @@ dmac: dma-controller@4330000 {
			snps,data-width = <2>;
			status = "disabled";
		};

		rtc@5025000 {
			compatible = "sophgo,cv1800b-rtc", "syscon";
			reg = <0x5025000 0x2000>;
			interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "alarm", "longpress", "vbat";
			clocks = <&clk CLK_RTC_25M>,
				 <&clk CLK_SRC_RTC_SYS_0>;
			clock-names = "rtc", "mcu";
		};
	};
};
+8 −0
Original line number Diff line number Diff line
@@ -55,6 +55,14 @@ &emmc {
	non-removable;
};

&gmac0 {
	status = "okay";
};

&mdio {
	status = "okay";
};

&sdhci0 {
	status = "okay";
	bus-width = <4>;
+98 −0
Original line number Diff line number Diff line
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
 */

#ifndef _SOPHGO_CV18XX_RESET
#define _SOPHGO_CV18XX_RESET

#define RST_DDR				2
#define RST_H264C			3
#define RST_JPEG			4
#define RST_H265C			5
#define RST_VIPSYS			6
#define RST_TDMA			7
#define RST_TPU				8
#define RST_TPUSYS			9
#define RST_USB				11
#define RST_ETH0			12
#define RST_ETH1			13
#define RST_NAND			14
#define RST_EMMC			15
#define RST_SD0				16
#define RST_SDMA			18
#define RST_I2S0			19
#define RST_I2S1			20
#define RST_I2S2			21
#define RST_I2S3			22
#define RST_UART0			23
#define RST_UART1			24
#define RST_UART2			25
#define RST_UART3			26
#define RST_I2C0			27
#define RST_I2C1			28
#define RST_I2C2			29
#define RST_I2C3			30
#define RST_I2C4			31
#define RST_PWM0			32
#define RST_PWM1			33
#define RST_PWM2			34
#define RST_PWM3			35
#define RST_SPI0			40
#define RST_SPI1			41
#define RST_SPI2			42
#define RST_SPI3			43
#define RST_GPIO0			44
#define RST_GPIO1			45
#define RST_GPIO2			46
#define RST_EFUSE			47
#define RST_WDT				48
#define RST_AHB_ROM			49
#define RST_SPIC			50
#define RST_TEMPSEN			51
#define RST_SARADC			52
#define RST_COMBO_PHY0			58
#define RST_SPI_NAND			61
#define RST_SE				62
#define RST_UART4			74
#define RST_GPIO3			75
#define RST_SYSTEM			76
#define RST_TIMER			77
#define RST_TIMER0			78
#define RST_TIMER1			79
#define RST_TIMER2			80
#define RST_TIMER3			81
#define RST_TIMER4			82
#define RST_TIMER5			83
#define RST_TIMER6			84
#define RST_TIMER7			85
#define RST_WGN0			86
#define RST_WGN1			87
#define RST_WGN2			88
#define RST_KEYSCAN			89
#define RST_AUDDAC			91
#define RST_AUDDAC_APB			92
#define RST_AUDADC			93
#define RST_VCSYS			95
#define RST_ETHPHY			96
#define RST_ETHPHY_APB			97
#define RST_AUDSRC			98
#define RST_VIP_CAM0			99
#define RST_WDT1			100
#define RST_WDT2			101
#define RST_AUTOCLEAR_CPUCORE0		256
#define RST_AUTOCLEAR_CPUCORE1		257
#define RST_AUTOCLEAR_CPUCORE2		258
#define RST_AUTOCLEAR_CPUCORE3		259
#define RST_AUTOCLEAR_CPUSYS0		260
#define RST_AUTOCLEAR_CPUSYS1		261
#define RST_AUTOCLEAR_CPUSYS2		262
#define RST_CPUCORE0			288
#define RST_CPUCORE1			289
#define RST_CPUCORE2			290
#define RST_CPUCORE3			291
#define RST_CPUSYS0			292
#define RST_CPUSYS1			293
#define RST_CPUSYS2			294

#endif /* _SOPHGO_CV18XX_RESET */
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