Commit 11b0567e authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: New interface adding PSR idle poll into dsb commit 



We are currently observing crc failures after we started using dsb for PSR
updates as well. This seems to happen because PSR HW is still sending
couple of updates using old framebuffers on wake-up.

This patch is preparing to fix that by adding interface which can be used
to add poll ensuring PSR HW is idle into dsb commit.

v3: add intel_dsb as a parameter to intel_psr_wait_for_idle_dsb
v2: add pass crtc_state->dsb_commit as parameter

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250905072708.2659411-4-jouni.hogander@intel.com
parent a0f7f3b1

drivers/gpu/drm/i915/display/intel_psr.c

+35 −4
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
#include "intel_dmc.h"

#include "intel_dp.h"

#include "intel_dp_aux.h"

#include "intel_dsb.h"

#include "intel_frontbuffer.h"

#include "intel_hdmi.h"

#include "intel_psr.h"
@@ -3006,7 +3007,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state, 
#define PSR_IDLE_TIMEOUT_MS 50



static int

_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)

_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,

				   struct intel_dsb *dsb)

{

	struct intel_display *display = to_intel_display(new_crtc_state);

	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -3016,6 +3018,13 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state 
	 * As all higher states has bit 4 of PSR2 state set we can just wait for

	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.

	 */

	if (dsb) {

		intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),

			       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200,

			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);

		return true;

	}



	return intel_de_wait_for_clear(display,

				       EDP_PSR2_STATUS(display, cpu_transcoder),

				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
@@ -3023,11 +3032,19 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state 
}



static int

_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)

_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,

				   struct intel_dsb *dsb)

{

	struct intel_display *display = to_intel_display(new_crtc_state);

	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;



	if (dsb) {

		intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),

			       EDP_PSR_STATUS_STATE_MASK, 0, 200,

			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);

		return true;

	}



	return intel_de_wait_for_clear(display,

				       psr_status_reg(display, cpu_transcoder),

				       EDP_PSR_STATUS_STATE_MASK,
@@ -3060,9 +3077,11 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat 
			continue;



		if (intel_dp->psr.sel_update_enabled)

			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state);

			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state,

								 NULL);

		else

			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state);

			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state,

								 NULL);



		if (ret)

			drm_err(display->drm,
@@ -3070,6 +3089,18 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat 
	}

}



void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb,

				 const struct intel_crtc_state *new_crtc_state)

{

	if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay)

		return;



	if (new_crtc_state->has_sel_update)

		_psr2_ready_for_pipe_update_locked(new_crtc_state, dsb);

	else

		_psr1_ready_for_pipe_update_locked(new_crtc_state, dsb);

}



static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ void intel_psr_get_config(struct intel_encoder *encoder, 
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);

void intel_psr_short_pulse(struct intel_dp *intel_dp);

void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);

void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb,

				 const struct intel_crtc_state *new_crtc_state);

bool intel_psr_enabled(struct intel_dp *intel_dp);

int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,

				struct intel_crtc *crtc);