Commit 11b5d56d authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'add-microchip-zl3073x-support-part-1' 

Ivan Vecera says:

====================
Add Microchip ZL3073x support (part 1)

Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP functionality. This series bring first part
that adds the core functionality and basic DPLL support.

The next part of the series will bring additional DPLL functionality
like eSync support, phase offset and frequency offset reporting and
phase adjustments.

Testing was done by myself and by Prathosh Satish on Microchip EDS2
development board with ZL30732 DPLL chip connected over I2C bus.
====================

Link: https://patch.msgid.link/20250704182202.1641943-1-ivecera@redhat.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents f47e8f61 ce26d7ca

Documentation/devicetree/bindings/dpll/dpll-device.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Digital Phase-Locked Loop (DPLL) Device



maintainers:

  - Ivan Vecera <ivecera@redhat.com>



description:

  Digital Phase-Locked Loop (DPLL) device is used for precise clock

  synchronization in networking and telecom hardware. The device can

  have one or more channels (DPLLs) and one or more physical input and

  output pins. Each DPLL channel can either produce pulse-per-clock signal

  or drive ethernet equipment clock. The type of each channel can be

  indicated by dpll-types property.



properties:

  $nodename:

    pattern: "^dpll(@.*)?$"



  "#address-cells":

    const: 0



  "#size-cells":

    const: 0



  dpll-types:

    description: List of DPLL channel types, one per DPLL instance.

    $ref: /schemas/types.yaml#/definitions/non-unique-string-array

    items:

      enum: [pps, eec]



  input-pins:

    type: object

    description: DPLL input pins

    unevaluatedProperties: false



    properties:

      "#address-cells":

        const: 1

      "#size-cells":

        const: 0



    patternProperties:

      "^pin@[0-9a-f]+$":

        $ref: /schemas/dpll/dpll-pin.yaml

        unevaluatedProperties: false



    required:

      - "#address-cells"

      - "#size-cells"



  output-pins:

    type: object

    description: DPLL output pins

    unevaluatedProperties: false



    properties:

      "#address-cells":

        const: 1

      "#size-cells":

        const: 0



    patternProperties:

      "^pin@[0-9]+$":

        $ref: /schemas/dpll/dpll-pin.yaml

        unevaluatedProperties: false



    required:

      - "#address-cells"

      - "#size-cells"



additionalProperties: true

Documentation/devicetree/bindings/dpll/dpll-pin.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: DPLL Pin



maintainers:

  - Ivan Vecera <ivecera@redhat.com>



description: |

  The DPLL pin is either a physical input or output pin that is provided

  by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by

  its physical order number that is stored in reg property and can have

  an additional set of properties like supported (allowed) frequencies,

  label, type and may support embedded sync.



  Note that the pin in this context has nothing to do with pinctrl.



properties:

  reg:

    description: Hardware index of the DPLL pin.

    maxItems: 1



  connection-type:

    description: Connection type of the pin

    $ref: /schemas/types.yaml#/definitions/string

    enum: [ext, gnss, int, mux, synce]



  esync-control:

    description: Indicates whether the pin supports embedded sync functionality.

    type: boolean



  label:

    description: String exposed as the pin board label

    $ref: /schemas/types.yaml#/definitions/string



  supported-frequencies-hz:

    description: List of supported frequencies for this pin, expressed in Hz.



required:

  - reg



additionalProperties: false

Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Azurite DPLL device



maintainers:

  - Ivan Vecera <ivecera@redhat.com>



description:

  Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that

  provides up to 5 independent DPLL channels, up to 10 differential or

  single-ended inputs and 10 differential or 20 single-ended outputs.

  These devices support both I2C and SPI interfaces.



properties:

  compatible:

    enum:

      - microchip,zl30731

      - microchip,zl30732

      - microchip,zl30733

      - microchip,zl30734

      - microchip,zl30735



  reg:

    maxItems: 1



required:

  - compatible

  - reg



allOf:

  - $ref: /schemas/dpll/dpll-device.yaml#

  - $ref: /schemas/spi/spi-peripheral-props.yaml#



unevaluatedProperties: false



examples:

  - |

    i2c {

      #address-cells = <1>;

      #size-cells = <0>;



      dpll@70 {

        compatible = "microchip,zl30732";

        reg = <0x70>;

        dpll-types = "pps", "eec";



        input-pins {

          #address-cells = <1>;

          #size-cells = <0>;



          pin@0 { /* REF0P */

            reg = <0>;

            connection-type = "ext";

            label = "Input 0";

            supported-frequencies-hz = /bits/ 64 <1 1000>;

          };

        };



        output-pins {

          #address-cells = <1>;

          #size-cells = <0>;



          pin@3 { /* OUT1N */

            reg = <3>;

            connection-type = "gnss";

            esync-control;

            label = "Output 1";

            supported-frequencies-hz = /bits/ 64 <1 10000>;

          };

        };

      };

    };

  - |

    spi {

      #address-cells = <1>;

      #size-cells = <0>;



      dpll@70 {

        compatible = "microchip,zl30731";

        reg = <0x70>;

        spi-max-frequency = <12500000>;



        dpll-types = "pps";



        input-pins {

          #address-cells = <1>;

          #size-cells = <0>;



          pin@0 { /* REF0P */

            reg = <0>;

            connection-type = "ext";

            label = "Input 0";

            supported-frequencies-hz = /bits/ 64 <1 1000>;

          };

        };



        output-pins {

          #address-cells = <1>;

          #size-cells = <0>;



          pin@3 { /* OUT1N */

            reg = <3>;

            connection-type = "gnss";

            esync-control;

            label = "Output 1";

            supported-frequencies-hz = /bits/ 64 <1 10000>;

          };

        };

      };

    };

...

Documentation/networking/devlink/devlink-params.rst

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@@ -140,3 +140,6 @@ own name. 
   * - ``enable_phc``

     - Boolean

     - Enable PHC (PTP Hardware Clock) functionality in the device.

   * - ``clock_id``

     - u64

     - Clock ID used by the device for registering DPLL devices and pins.

Documentation/networking/devlink/index.rst

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@@ -98,3 +98,4 @@ parameters, info versions, and other features it supports. 
   iosm

   octeontx2

   sfc

   zl3073x