Commit 11d672db authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Update DCN401 path for cursor offload 



[Description]
The DCN401 cursor offload path needs to take into account
use_mall_for_cursor, and also need to ensure the dcn32
function assigns the cursor cache fields (DCN401 uses the
dcn32 implementation).

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d7f5a61e

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

+43 −27
Original line number Diff line number Diff line
@@ -118,9 +118,29 @@ void hubp32_cursor_set_attributes( 
	uint32_t cursor_width = ((attr->width + 63) / 64) * 64;

	uint32_t cursor_height = attr->height;

	uint32_t cursor_size = cursor_width * cursor_height;

	bool use_mall_for_cursor;



	switch (attr->color_format) {

	case CURSOR_MODE_MONO:

		cursor_size /= 2;

		break;

	case CURSOR_MODE_COLOR_1BIT_AND:

	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:

	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:

		cursor_size *= 4;

		break;



	case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:

	case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:

	default:

		cursor_size *= 8;

		break;

	}

	use_mall_for_cursor = cursor_size > 16384 ? 1 : 0;



	hubp->curs_attr = *attr;



	if (!hubp->cursor_offload) {

		REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

				CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);

		REG_UPDATE(CURSOR_SURFACE_ADDRESS,
@@ -142,27 +162,23 @@ void hubp32_cursor_set_attributes( 
				 /* used to shift the cursor chunk request deadline */

				CURSOR0_CHUNK_HDL_ADJUST, 3);



	switch (attr->color_format) {

	case CURSOR_MODE_MONO:

		cursor_size /= 2;

		break;

	case CURSOR_MODE_COLOR_1BIT_AND:

	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:

	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:

		cursor_size *= 4;

		break;



	case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:

	case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:

	default:

		cursor_size *= 8;

		break;

		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, use_mall_for_cursor);

	}



	if (cursor_size > 16384)

		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);

	else

		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);

	hubp->att.SURFACE_ADDR_HIGH  = attr->address.high_part;

	hubp->att.SURFACE_ADDR       = attr->address.low_part;

	hubp->att.size.bits.width    = attr->width;

	hubp->att.size.bits.height   = attr->height;

	hubp->att.cur_ctl.bits.mode  = attr->color_format;



	hubp->cur_rect.w = attr->width;

	hubp->cur_rect.h = attr->height;



	hubp->att.cur_ctl.bits.pitch = hw_pitch;

	hubp->att.cur_ctl.bits.line_per_chunk = lpc;

	hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

	hubp->att.settings.bits.dst_y_offset  = 0;

	hubp->att.settings.bits.chunk_hdl_adjust = 3;

	hubp->use_mall_for_cursor = use_mall_for_cursor;

}

void hubp32_init(struct hubp *hubp)

{

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -2727,6 +2727,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip 


	p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;

	p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;

	p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor;



	cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx);

}

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

+1 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ struct hubp { 
	struct cursor_position_cache_hubp  pos;

	struct cursor_attribute_cache_hubp att;

	struct cursor_rect cur_rect;

	bool use_mall_for_cursor;

};



struct surface_flip_registers {