Commit 11eaac6e authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.11-tag3' of... 

Merge tag 'renesas-pinctrl-for-v6.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

pinctrl: renesas: Updates for v6.11 (take three)

  - Support output enable on RZ/G2L.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 30b7748b 2453e858

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+95 −49
Original line number Diff line number Diff line
@@ -294,8 +294,8 @@ struct rzg2l_pinctrl_data { 
#endif

	void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);

	void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);

	u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);

	int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);

	u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);

	int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);

	int (*hw_to_bias_param)(unsigned int val);

	int (*bias_param_to_hw)(enum pin_config_param param);

};
@@ -999,53 +999,100 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 
	return false;

}



static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)

static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	if (!(caps & PIN_CFG_OEN))

		return false;

	u64 *pin_data = pctrl->desc.pins[_pin].drv_data;

	u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);

	u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);



	if (pin > max_pin)

		return false;

	if (pin > pctrl->data->hwcfg->oen_max_pin)

		return -EINVAL;



	return true;

	/*

	 * We can determine which Ethernet interface we're dealing with from

	 * the caps.

	 */

	if (caps & PIN_CFG_IO_VMC_ETH0)

		return 0;

	if (caps & PIN_CFG_IO_VMC_ETH1)

		return 1;



	return -EINVAL;

}



static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)

static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	if (pin)

		pin *= 2;

	int bit;



	if (offset / RZG2L_PINS_PER_PORT == max_port)

		pin += 1;

	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return 0;



	return pin;

	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));

}



static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)

static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	u8 max_port = pctrl->data->hwcfg->oen_max_port;

	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;

	u8 bit;

	unsigned long flags;

	int bit;

	u8 val;



	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;



	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + ETH_MODE);

	if (oen)

		val &= ~BIT(bit);

	else

		val |= BIT(bit);

	writeb(val, pctrl->base + ETH_MODE);

	spin_unlock_irqrestore(&pctrl->lock, flags);



	if (!rzg2l_oen_is_supported(caps, pin, max_pin))

	return 0;

}



static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	u64 *pin_data = pctrl->desc.pins[_pin].drv_data;

	u8 port, pin, bit;



	if (*pin_data & RZG2L_SINGLE_PIN)

		return -EINVAL;



	port = RZG2L_PIN_ID_TO_PORT(_pin);

	pin = RZG2L_PIN_ID_TO_PIN(_pin);

	if (pin > pctrl->data->hwcfg->oen_max_pin)

		return -EINVAL;



	bit = pin * 2;

	if (port == pctrl->data->hwcfg->oen_max_port)

		bit += 1;



	return bit;

}



static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	int bit;



	bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);

	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;



	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));

}



static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)

static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	u8 max_port = pctrl->data->hwcfg->oen_max_port;

	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;

	unsigned long flags;

	u8 val, bit;



	if (!rzg2l_oen_is_supported(caps, pin, max_pin))

		return -EINVAL;

	int bit;

	u8 val;



	bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);

	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;



	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + ETH_MODE);
@@ -1124,12 +1171,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param) 
	return -EINVAL;

}



static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)

static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",

						  "XSPI0_RESET0N", "XSPI0_CS0N",

						  "XSPI0_CKN", "XSPI0_CKP" };

	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];

	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];

	unsigned int i;



	for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
@@ -1141,19 +1188,16 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset) 
	return 0;

}



static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)

static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	u8 bit;



	if (!(caps & PIN_CFG_OEN))

		return 0;



	bit = rzv2h_pin_to_oen_bit(pctrl, offset);

	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);



	return !(readb(pctrl->base + PFC_OEN) & BIT(bit));

}



static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)

static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;

	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
@@ -1161,10 +1205,7 @@ static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 
	u8 val, bit;

	u8 pwpr;



	if (!(caps & PIN_CFG_OEN))

		return -EINVAL;



	bit = rzv2h_pin_to_oen_bit(pctrl, offset);

	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);

	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + PFC_OEN);

	if (oen)
@@ -1220,7 +1261,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
		break;



	case PIN_CONFIG_OUTPUT_ENABLE:

		arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);

		if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))

			return -EOPNOTSUPP;

		arg = pctrl->data->oen_read(pctrl, _pin);

		if (!arg)

			return -EINVAL;

		break;
@@ -1359,7 +1402,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 


		case PIN_CONFIG_OUTPUT_ENABLE:

			arg = pinconf_to_config_argument(_configs[i]);

			ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);

			if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))

				return -EOPNOTSUPP;

			ret = pctrl->data->oen_write(pctrl, _pin, !!arg);

			if (ret)

				return ret;

			break;
@@ -1784,7 +1829,7 @@ static const u64 r9a07g044_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),

	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -1793,7 +1838,7 @@ static const u64 r9a07g044_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),

	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -1817,13 +1862,13 @@ static const u64 r9a07g044_gpio_configs[] = { 


static const u64 r9a07g043_gpio_configs[] = {

	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),

	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),

	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -3016,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { 
		[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,

	},

	.iolh_groupb_oi = { 100, 66, 50, 33, },

	.oen_max_pin = 0,

};



static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3103,8 +3149,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { 
	.hwcfg = &rzg3s_hwcfg,

	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzg2l_pmc_writeb,

	.oen_read = &rzg2l_read_oen,

	.oen_write = &rzg2l_write_oen,

	.oen_read = &rzg3s_oen_read,

	.oen_write = &rzg3s_oen_write,

	.hw_to_bias_param = &rzg2l_hw_to_bias_param,

	.bias_param_to_hw = &rzg2l_bias_param_to_hw,

};