Commit 11f56332 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.8-2' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.8 part #2

- Zbc extension support for Guest/VM
- Scalar crypto extensions support for Guest/VM
- Vector crypto extensions support for Guest/VM
- Zfh[min] extensions support for Guest/VM
- Zihintntl extension support for Guest/VM
- Zvfh[min] extensions support for Guest/VM
- Zfa extension support for Guest/VM
parents 3f5198c7 4d0e8f9a

arch/riscv/include/uapi/asm/kvm.h

+27 −0
Original line number Diff line number Diff line
@@ -139,6 +139,33 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_ZIHPM,

	KVM_RISCV_ISA_EXT_SMSTATEEN,

	KVM_RISCV_ISA_EXT_ZICOND,

	KVM_RISCV_ISA_EXT_ZBC,

	KVM_RISCV_ISA_EXT_ZBKB,

	KVM_RISCV_ISA_EXT_ZBKC,

	KVM_RISCV_ISA_EXT_ZBKX,

	KVM_RISCV_ISA_EXT_ZKND,

	KVM_RISCV_ISA_EXT_ZKNE,

	KVM_RISCV_ISA_EXT_ZKNH,

	KVM_RISCV_ISA_EXT_ZKR,

	KVM_RISCV_ISA_EXT_ZKSED,

	KVM_RISCV_ISA_EXT_ZKSH,

	KVM_RISCV_ISA_EXT_ZKT,

	KVM_RISCV_ISA_EXT_ZVBB,

	KVM_RISCV_ISA_EXT_ZVBC,

	KVM_RISCV_ISA_EXT_ZVKB,

	KVM_RISCV_ISA_EXT_ZVKG,

	KVM_RISCV_ISA_EXT_ZVKNED,

	KVM_RISCV_ISA_EXT_ZVKNHA,

	KVM_RISCV_ISA_EXT_ZVKNHB,

	KVM_RISCV_ISA_EXT_ZVKSED,

	KVM_RISCV_ISA_EXT_ZVKSH,

	KVM_RISCV_ISA_EXT_ZVKT,

	KVM_RISCV_ISA_EXT_ZFH,

	KVM_RISCV_ISA_EXT_ZFHMIN,

	KVM_RISCV_ISA_EXT_ZIHINTNTL,

	KVM_RISCV_ISA_EXT_ZVFH,

	KVM_RISCV_ISA_EXT_ZVFHMIN,

	KVM_RISCV_ISA_EXT_ZFA,

	KVM_RISCV_ISA_EXT_MAX,

};

arch/riscv/kvm/vcpu_onereg.c

+54 −0
Original line number Diff line number Diff line
@@ -42,15 +42,42 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(SVPBMT),

	KVM_ISA_EXT_ARR(ZBA),

	KVM_ISA_EXT_ARR(ZBB),

	KVM_ISA_EXT_ARR(ZBC),

	KVM_ISA_EXT_ARR(ZBKB),

	KVM_ISA_EXT_ARR(ZBKC),

	KVM_ISA_EXT_ARR(ZBKX),

	KVM_ISA_EXT_ARR(ZBS),

	KVM_ISA_EXT_ARR(ZFA),

	KVM_ISA_EXT_ARR(ZFH),

	KVM_ISA_EXT_ARR(ZFHMIN),

	KVM_ISA_EXT_ARR(ZICBOM),

	KVM_ISA_EXT_ARR(ZICBOZ),

	KVM_ISA_EXT_ARR(ZICNTR),

	KVM_ISA_EXT_ARR(ZICOND),

	KVM_ISA_EXT_ARR(ZICSR),

	KVM_ISA_EXT_ARR(ZIFENCEI),

	KVM_ISA_EXT_ARR(ZIHINTNTL),

	KVM_ISA_EXT_ARR(ZIHINTPAUSE),

	KVM_ISA_EXT_ARR(ZIHPM),

	KVM_ISA_EXT_ARR(ZKND),

	KVM_ISA_EXT_ARR(ZKNE),

	KVM_ISA_EXT_ARR(ZKNH),

	KVM_ISA_EXT_ARR(ZKR),

	KVM_ISA_EXT_ARR(ZKSED),

	KVM_ISA_EXT_ARR(ZKSH),

	KVM_ISA_EXT_ARR(ZKT),

	KVM_ISA_EXT_ARR(ZVBB),

	KVM_ISA_EXT_ARR(ZVBC),

	KVM_ISA_EXT_ARR(ZVFH),

	KVM_ISA_EXT_ARR(ZVFHMIN),

	KVM_ISA_EXT_ARR(ZVKB),

	KVM_ISA_EXT_ARR(ZVKG),

	KVM_ISA_EXT_ARR(ZVKNED),

	KVM_ISA_EXT_ARR(ZVKNHA),

	KVM_ISA_EXT_ARR(ZVKNHB),

	KVM_ISA_EXT_ARR(ZVKSED),

	KVM_ISA_EXT_ARR(ZVKSH),

	KVM_ISA_EXT_ARR(ZVKT),

};



static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -92,13 +119,40 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_SVNAPOT:

	case KVM_RISCV_ISA_EXT_ZBA:

	case KVM_RISCV_ISA_EXT_ZBB:

	case KVM_RISCV_ISA_EXT_ZBC:

	case KVM_RISCV_ISA_EXT_ZBKB:

	case KVM_RISCV_ISA_EXT_ZBKC:

	case KVM_RISCV_ISA_EXT_ZBKX:

	case KVM_RISCV_ISA_EXT_ZBS:

	case KVM_RISCV_ISA_EXT_ZFA:

	case KVM_RISCV_ISA_EXT_ZFH:

	case KVM_RISCV_ISA_EXT_ZFHMIN:

	case KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_RISCV_ISA_EXT_ZICOND:

	case KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_RISCV_ISA_EXT_ZIHINTNTL:

	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:

	case KVM_RISCV_ISA_EXT_ZIHPM:

	case KVM_RISCV_ISA_EXT_ZKND:

	case KVM_RISCV_ISA_EXT_ZKNE:

	case KVM_RISCV_ISA_EXT_ZKNH:

	case KVM_RISCV_ISA_EXT_ZKR:

	case KVM_RISCV_ISA_EXT_ZKSED:

	case KVM_RISCV_ISA_EXT_ZKSH:

	case KVM_RISCV_ISA_EXT_ZKT:

	case KVM_RISCV_ISA_EXT_ZVBB:

	case KVM_RISCV_ISA_EXT_ZVBC:

	case KVM_RISCV_ISA_EXT_ZVFH:

	case KVM_RISCV_ISA_EXT_ZVFHMIN:

	case KVM_RISCV_ISA_EXT_ZVKB:

	case KVM_RISCV_ISA_EXT_ZVKG:

	case KVM_RISCV_ISA_EXT_ZVKNED:

	case KVM_RISCV_ISA_EXT_ZVKNHA:

	case KVM_RISCV_ISA_EXT_ZVKNHB:

	case KVM_RISCV_ISA_EXT_ZVKSED:

	case KVM_RISCV_ISA_EXT_ZVKSH:

	case KVM_RISCV_ISA_EXT_ZVKT:

		return false;

	/* Extensions which can be disabled using Smstateen */

	case KVM_RISCV_ISA_EXT_SSAIA:

tools/testing/selftests/kvm/riscv/get-reg-list.c

+108 −0
Original line number Diff line number Diff line
@@ -49,15 +49,42 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:

	/*

	 * Like ISA_EXT registers, SBI_EXT registers are only visible when the

	 * host supports them and disabling them does not affect the visibility
@@ -394,15 +421,42 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) 
		KVM_ISA_EXT_ARR(SVPBMT),

		KVM_ISA_EXT_ARR(ZBA),

		KVM_ISA_EXT_ARR(ZBB),

		KVM_ISA_EXT_ARR(ZBC),

		KVM_ISA_EXT_ARR(ZBKB),

		KVM_ISA_EXT_ARR(ZBKC),

		KVM_ISA_EXT_ARR(ZBKX),

		KVM_ISA_EXT_ARR(ZBS),

		KVM_ISA_EXT_ARR(ZFA),

		KVM_ISA_EXT_ARR(ZFH),

		KVM_ISA_EXT_ARR(ZFHMIN),

		KVM_ISA_EXT_ARR(ZICBOM),

		KVM_ISA_EXT_ARR(ZICBOZ),

		KVM_ISA_EXT_ARR(ZICNTR),

		KVM_ISA_EXT_ARR(ZICOND),

		KVM_ISA_EXT_ARR(ZICSR),

		KVM_ISA_EXT_ARR(ZIFENCEI),

		KVM_ISA_EXT_ARR(ZIHINTNTL),

		KVM_ISA_EXT_ARR(ZIHINTPAUSE),

		KVM_ISA_EXT_ARR(ZIHPM),

		KVM_ISA_EXT_ARR(ZKND),

		KVM_ISA_EXT_ARR(ZKNE),

		KVM_ISA_EXT_ARR(ZKNH),

		KVM_ISA_EXT_ARR(ZKR),

		KVM_ISA_EXT_ARR(ZKSED),

		KVM_ISA_EXT_ARR(ZKSH),

		KVM_ISA_EXT_ARR(ZKT),

		KVM_ISA_EXT_ARR(ZVBB),

		KVM_ISA_EXT_ARR(ZVBC),

		KVM_ISA_EXT_ARR(ZVFH),

		KVM_ISA_EXT_ARR(ZVFHMIN),

		KVM_ISA_EXT_ARR(ZVKB),

		KVM_ISA_EXT_ARR(ZVKG),

		KVM_ISA_EXT_ARR(ZVKNED),

		KVM_ISA_EXT_ARR(ZVKNHA),

		KVM_ISA_EXT_ARR(ZVKNHB),

		KVM_ISA_EXT_ARR(ZVKSED),

		KVM_ISA_EXT_ARR(ZVKSH),

		KVM_ISA_EXT_ARR(ZVKT),

	};



	if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
@@ -888,15 +942,42 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); 
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);

KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);

KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);

KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);

KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);

KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);

KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);

KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);

KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);

KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);

KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);

KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);

KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);

KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);

KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);

KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);

KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);

KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);

KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);

KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);

KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);

KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);

KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH);

KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);

KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);

KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);

KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);

KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);

KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);

KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);

KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);

KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);

KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);

KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);

KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);



struct vcpu_reg_list *vcpu_configs[] = {

	&config_sbi_base,
@@ -914,14 +995,41 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&config_svpbmt,

	&config_zba,

	&config_zbb,

	&config_zbc,

	&config_zbkb,

	&config_zbkc,

	&config_zbkx,

	&config_zbs,

	&config_zfa,

	&config_zfh,

	&config_zfhmin,

	&config_zicbom,

	&config_zicboz,

	&config_zicntr,

	&config_zicond,

	&config_zicsr,

	&config_zifencei,

	&config_zihintntl,

	&config_zihintpause,

	&config_zihpm,

	&config_zknd,

	&config_zkne,

	&config_zknh,

	&config_zkr,

	&config_zksed,

	&config_zksh,

	&config_zkt,

	&config_zvbb,

	&config_zvbc,

	&config_zvfh,

	&config_zvfhmin,

	&config_zvkb,

	&config_zvkg,

	&config_zvkned,

	&config_zvknha,

	&config_zvknhb,

	&config_zvksed,

	&config_zvksh,

	&config_zvkt,

};

int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);