Commit 121f17ac authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amd/pm: enable more Pstates profile levels for SMU v13.0.5 



This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.

- profile_peak
- profile_min_sclk
- profile_standard

Signed-off-by: default avatarTim Huang <Tim.Huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fdc95df9

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

+38 −2
Original line number Diff line number Diff line
@@ -978,6 +978,38 @@ static int smu_v13_0_5_force_clk_levels(struct smu_context *smu, 
	return ret;

}



static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,

					enum amd_dpm_forced_level level,

					enum smu_clk_type clk_type,

					uint32_t *min_clk,

					uint32_t *max_clk)

{

	int ret = 0;

	uint32_t clk_limit = 0;



	switch (clk_type) {

	case SMU_GFXCLK:

	case SMU_SCLK:

		clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;

		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)

			smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);

		else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)

			smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);

		break;

	case SMU_VCLK:

		smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);

		break;

	case SMU_DCLK:

		smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);

		break;

	default:

		ret = -EINVAL;

		break;

	}

	*min_clk = *max_clk = clk_limit;

	return ret;

}



static int smu_v13_0_5_set_performance_level(struct smu_context *smu,

						enum amd_dpm_forced_level level)

{
@@ -1011,10 +1043,14 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu, 
		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

		/* Temporarily do nothing since the optimal clocks haven't been provided yet */

		smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);

		smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);

		smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

		dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");

		return -EOPNOTSUPP;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:

		return 0;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h

+1 −1
Original line number Diff line number Diff line
@@ -24,6 +24,6 @@ 
#define __SMU_V13_0_5_PPT_H__



extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);

#define SMU_13_0_5_UMD_PSTATE_GFXCLK   1100

#define SMU_13_0_5_UMD_PSTATE_GFXCLK   700



#endif