Commit 1288d702 authored by Duncan Ma's avatar Duncan Ma Committed by Alex Deucher
Browse files

drm/amd/display: Improve x86 and dmub ips handshake 



[Why]
There is a race condition between x86 and dmcub fw when attempting to exit
IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This
can cause unexpected hang when DMCUB attempt to exit while PMFW still
tries to enter IPS2.

[How]
A new design has been introduced to remove race conditions and improve the
handshake between x86 and DMCUB. An AON scratch register is borrowed from
PMFW to determine whether DMCUB has committed to IPS entry or not.

In the case when dmcub has committed IPS entry, x86 must poll until an exit
event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait
upperbound of evaluation and IPS entry time to ensure IPS2 exit event has
been sent to PMFW.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarDuncan Ma <duncan.ma@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 786d3b1d

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+37 −0
Original line number Diff line number Diff line
@@ -738,6 +738,34 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base) 
	}

}



static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dc *dc = clk_mgr_base->ctx->dc;

	uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);



	if (dc->debug.disable_ips == 0) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS1) {

		val = val & ~DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

		val |= DMUB_IPS1_ALLOW_MASK;

		val |= DMUB_IPS2_ALLOW_MASK;

	}



	if (!allow_idle) {

		val = val & ~DMUB_IPS1_ALLOW_MASK;

		val = val & ~DMUB_IPS2_ALLOW_MASK;

	}



	dcn35_smu_write_ips_scratch(clk_mgr, val);

}



static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -757,6 +785,13 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) 
	return ips_supported;

}



static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);



	return dcn35_smu_read_ips_scratch(clk_mgr);

}



static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)

{

	dcn35_init_clocks(clk_mgr);
@@ -844,6 +879,8 @@ static struct clk_mgr_funcs dcn35_funcs = { 
	.set_low_power_state = dcn35_set_low_power_state,

	.exit_low_power_state = dcn35_exit_low_power_state,

	.is_ips_supported = dcn35_is_ips_supported,

	.set_idle_state = dcn35_set_idle_state,

	.get_idle_state = dcn35_get_idle_state

};



struct clk_mgr_funcs dcn35_fpga_funcs = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

+12 −2
Original line number Diff line number Diff line
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl 
			enable);

}



void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

{

	dcn35_smu_send_msg_with_param(

	return dcn35_smu_send_msg_with_param(

		clk_mgr,

		VBIOSSMC_MSG_DispPsrExit,

		0);
@@ -459,3 +459,13 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) 
			VBIOSSMC_MSG_QueryIPS2Support,

			0);

}



void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)

{

	REG_WRITE(MP1_SMN_C2PMSG_71, param);

}



uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)

{

	return REG_READ(MP1_SMN_C2PMSG_71);

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

+3 −1
Original line number Diff line number Diff line
@@ -174,8 +174,10 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst 
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);



void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);

uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);

#endif /* DAL_DC_35_SMU_H_ */

drivers/gpu/drm/amd/display/dc/dc.h

+2 −0
Original line number Diff line number Diff line
@@ -965,6 +965,8 @@ struct dc_debug_options { 
	bool replay_skip_crtc_disabled;

	bool ignore_pg;/*do nothing, let pmfw control it*/

	bool psp_disabled_wa;

	unsigned int ips2_eval_delay_us;

	unsigned int ips2_entry_delay_us;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+45 −12
Original line number Diff line number Diff line
@@ -1100,31 +1100,64 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) 


	cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;



	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

	if (allow_idle) {

		if (dc->hwss.set_idle_state)

			dc->hwss.set_idle_state(dc, true);

	}



	if (allow_idle)

		udelay(500);

	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



void dc_dmub_srv_exit_low_power_state(const struct dc *dc)

{

	uint32_t allow_state = 0;

	uint32_t commit_state = 0;



	if (dc->debug.dmcub_emulation)

		return;



	if (!dc->idle_optimizations_allowed)

		return;



	if (dc->hwss.get_idle_state &&

		dc->hwss.set_idle_state &&

		dc->clk_mgr->funcs->exit_low_power_state) {



		allow_state = dc->hwss.get_idle_state(dc);

		dc->hwss.set_idle_state(dc, false);



		if (allow_state & DMUB_IPS2_ALLOW_MASK) {

			// Wait for evaluation time

			udelay(dc->debug.ips2_eval_delay_us);

			commit_state = dc->hwss.get_idle_state(dc);

			if (commit_state & DMUB_IPS2_COMMIT_MASK) {

				// Tell PMFW to exit low power state

	if (dc->clk_mgr->funcs->exit_low_power_state)

				dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);



	// Wait for dmcub to load up

	dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);

				// Wait for IPS2 entry upper bound

				udelay(dc->debug.ips2_entry_delay_us);

				dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);



				do {

					commit_state = dc->hwss.get_idle_state(dc);

				} while (commit_state & DMUB_IPS2_COMMIT_MASK);



				if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

					ASSERT(0);



				return;

			}

		}



	// Notify dmcub disallow idle

		dc_dmub_srv_notify_idle(dc, false);

		if (allow_state & DMUB_IPS1_ALLOW_MASK) {

			do {

				commit_state = dc->hwss.get_idle_state(dc);

			} while (commit_state & DMUB_IPS1_COMMIT_MASK);

		}

	}



	// Confirm dmu is powered up

	dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);

	if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

		ASSERT(0);

}