Commit 128c20ed authored by Nirmoy Das's avatar Nirmoy Das Committed by Rodrigo Vivi
Browse files

drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval 



PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.

Fixes: 78a6ccd6 ("drm/i915/gt: Ensure memory quiesced before invalidation")
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Mark Janes <mark.janes@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Acked-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Tested-by: default avatarTapani Pälli <tapani.palli@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230926142401.25687-1-nirmoy.das@intel.com


(cherry picked from commit 03d68141)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 8a749fd1

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+10 −1
Original line number Diff line number Diff line
@@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))

			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		/*

		 * L3 fabric flush is needed for AUX CCS invalidation

		 * which happens as part of pipe-control so we can

		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3

		 * deals with Protected Memory which is not needed for

		 * AUX CCS invalidation and lead to unwanted side effects.

		 */

		if (mode & EMIT_FLUSH)

			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		/* Wa_1409600907:tgl,adl-p */