Commit 12d74553 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Move pipe_offsets[] & co. to INTEL_INFO->display 



The display register offsets are display stuff so stick
into the display portion of the device info.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 04155815

drivers/gpu/drm/i915/i915_pci.c

+22 −22
Original line number Diff line number Diff line
@@ -38,43 +38,43 @@ 
	.display.ver = (x)



#define I845_PIPE_OFFSETS \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET,	\

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

	}



#define I9XX_PIPE_OFFSETS \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET,	\

		[TRANSCODER_B] = PIPE_B_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

	}



#define IVB_PIPE_OFFSETS \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET,	\

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \

	}



#define HSW_PIPE_OFFSETS \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET,	\

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \

		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -82,44 +82,44 @@ 
	}



#define CHV_PIPE_OFFSETS \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET, \

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \

	}



#define I845_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

	}



#define I9XX_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

		[PIPE_B] = CURSOR_B_OFFSET, \

	}



#define CHV_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

		[PIPE_B] = CURSOR_B_OFFSET, \

		[PIPE_C] = CHV_CURSOR_C_OFFSET, \

	}



#define IVB_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

		[PIPE_B] = IVB_CURSOR_B_OFFSET, \

		[PIPE_C] = IVB_CURSOR_C_OFFSET, \

	}



#define TGL_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

		[PIPE_B] = IVB_CURSOR_B_OFFSET, \

		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -801,7 +801,7 @@ static const struct intel_device_info cml_gt2_info = { 
	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \

		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET, \

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -809,7 +809,7 @@ static const struct intel_device_info cml_gt2_info = { 
		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \

		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -854,7 +854,7 @@ static const struct intel_device_info jsl_info = { 
	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \

		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \

	.pipe_offsets = { \

	.display.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET, \

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -862,7 +862,7 @@ static const struct intel_device_info jsl_info = { 
		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \

		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \

	}, \

	.trans_offsets = { \

	.display.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -929,7 +929,7 @@ static const struct intel_device_info adl_s_info = { 
};



#define XE_LPD_CURSOR_OFFSETS \

	.cursor_offsets = { \

	.display.cursor_offsets = { \

		[PIPE_A] = CURSOR_A_OFFSET, \

		[PIPE_B] = IVB_CURSOR_B_OFFSET, \

		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -958,7 +958,7 @@ static const struct intel_device_info adl_s_info = { 
	.display.has_psr = 1,							\

	.display.ver = 13,							\

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\

	.pipe_offsets = {							\

	.display.pipe_offsets = {						\

		[TRANSCODER_A] = PIPE_A_OFFSET,					\

		[TRANSCODER_B] = PIPE_B_OFFSET,					\

		[TRANSCODER_C] = PIPE_C_OFFSET,					\
@@ -966,7 +966,7 @@ static const struct intel_device_info adl_s_info = { 
		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\

		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\

	},									\

	.trans_offsets = {							\

	.display.trans_offsets = {						\

		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\

		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\

		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\

drivers/gpu/drm/i915/i915_reg.h

+9 −9
Original line number Diff line number Diff line
@@ -161,16 +161,16 @@ 
 * Device info offset array based helpers for groups of registers with unevenly

 * spaced base offsets.

 */

#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \

					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \

					      DISPLAY_MMIO_BASE(dev_priv))

#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \

					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \

					 DISPLAY_MMIO_BASE(dev_priv))

#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \

					 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \

					 DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))

#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \

					      DISPLAY_MMIO_BASE(dev_priv))

#define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))



#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))

#define _MASKED_FIELD(mask, value) ({					   \

drivers/gpu/drm/i915/intel_device_info.h

+5 −5
Original line number Diff line number Diff line
@@ -233,13 +233,13 @@ struct intel_device_info { 
#define DEFINE_FLAG(name) u8 name:1

		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);

#undef DEFINE_FLAG

	} display;





		/* Register offsets for the various display pipes and transcoders */

		int pipe_offsets[I915_MAX_TRANSCODERS];

		int trans_offsets[I915_MAX_TRANSCODERS];

		int cursor_offsets[I915_MAX_PIPES];

	} display;





	struct color_luts {

		u32 degamma_lut_size;