Commit 12e3c55d authored by Wolfram Sang's avatar Wolfram Sang Committed by Ulf Hansson
Browse files

mmc: renesas_sdhi: remove 4taps as a TMIO flag 



Now that the quirks structure is accessible, we can remove the TMIO flag
for HS400 using only 4 taps. This is Renesas specific anyhow.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191203200513.1758-5-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 7af08206

drivers/mmc/host/renesas_sdhi_core.c

+2 −5
Original line number Diff line number Diff line
@@ -350,7 +350,7 @@ static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) 
		       0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);





	if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)

	if (priv->quirks && priv->quirks->hs400_4taps)

		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,

			       host->tap_set / 2);
@@ -488,7 +488,7 @@ static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 
static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)

{

	struct renesas_sdhi *priv = host_to_priv(host);

	bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;

	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;



	/*

	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
@@ -720,9 +720,6 @@ int renesas_sdhi_probe(struct platform_device *pdev, 
	if (quirks && quirks->hs400_disabled)

		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);



	if (quirks && quirks->hs400_4taps)

		mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400;



	/* For some SoC, we disable internal WP. GPIO may override this */

	if (mmc_can_gpio_ro(host->mmc))

		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;

include/linux/mfd/tmio.h

+0 −3
Original line number Diff line number Diff line
@@ -79,9 +79,6 @@ 
/* Some controllers have a CBSY bit */

#define TMIO_MMC_HAVE_CBSY		BIT(11)



/* Some controllers that support HS400 use 4 taps while others use 8. */

#define TMIO_MMC_HAVE_4TAP_HS400	BIT(13)



int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);

int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);

void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);