Loading arch/mips/lasat/setup.c +0 −1 Original line number Diff line number Diff line Loading @@ -116,7 +116,6 @@ static void lasat_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); } Loading arch/mips/mips-boards/generic/time.c +0 −3 Original line number Diff line number Diff line Loading @@ -295,7 +295,4 @@ void __init plat_timer_setup(struct irqaction *irq) irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); } arch/mips/mips-boards/sim/sim_time.c +0 −3 Original line number Diff line number Diff line Loading @@ -199,7 +199,4 @@ void __init plat_timer_setup(struct irqaction *irq) irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); } arch/mips/tx4927/common/tx4927_setup.c +0 −10 Original line number Diff line number Diff line Loading @@ -81,18 +81,8 @@ void __init tx4927_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { u32 count; u32 c1; u32 c2; setup_irq(TX4927_IRQ_CPU_TIMER, irq); /* to generate the first timer interrupt */ c1 = read_c0_count(); count = c1 + (mips_hpt_frequency / HZ); write_c0_compare(count); c2 = read_c0_count(); #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_timer_setup(struct irqaction Loading arch/mips/tx4938/common/setup.c +0 −9 Original line number Diff line number Diff line Loading @@ -55,14 +55,5 @@ tx4938_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { u32 count; u32 c1; u32 c2; setup_irq(TX4938_IRQ_CPU_TIMER, irq); c1 = read_c0_count(); count = c1 + (mips_hpt_frequency / HZ); write_c0_compare(count); c2 = read_c0_count(); } Loading
arch/mips/lasat/setup.c +0 −1 Original line number Diff line number Diff line Loading @@ -116,7 +116,6 @@ static void lasat_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); } Loading
arch/mips/mips-boards/generic/time.c +0 −3 Original line number Diff line number Diff line Loading @@ -295,7 +295,4 @@ void __init plat_timer_setup(struct irqaction *irq) irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); }
arch/mips/mips-boards/sim/sim_time.c +0 −3 Original line number Diff line number Diff line Loading @@ -199,7 +199,4 @@ void __init plat_timer_setup(struct irqaction *irq) irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); #endif /* to generate the first timer interrupt */ write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); }
arch/mips/tx4927/common/tx4927_setup.c +0 −10 Original line number Diff line number Diff line Loading @@ -81,18 +81,8 @@ void __init tx4927_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { u32 count; u32 c1; u32 c2; setup_irq(TX4927_IRQ_CPU_TIMER, irq); /* to generate the first timer interrupt */ c1 = read_c0_count(); count = c1 + (mips_hpt_frequency / HZ); write_c0_compare(count); c2 = read_c0_count(); #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_timer_setup(struct irqaction Loading
arch/mips/tx4938/common/setup.c +0 −9 Original line number Diff line number Diff line Loading @@ -55,14 +55,5 @@ tx4938_time_init(void) void __init plat_timer_setup(struct irqaction *irq) { u32 count; u32 c1; u32 c2; setup_irq(TX4938_IRQ_CPU_TIMER, irq); c1 = read_c0_count(); count = c1 + (mips_hpt_frequency / HZ); write_c0_compare(count); c2 = read_c0_count(); }