Commit 13327fad authored by Xin Li (Intel)'s avatar Xin Li (Intel) Committed by Borislav Petkov (AMD)
Browse files

x86/cpufeatures: Shorten X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT 



Shorten X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT to
X86_FEATURE_CLEAR_BHB_VMEXIT to make the last column aligned
consistently in the whole file.

There's no need to explain in the name what the mitigation does.

No functional changes.

Suggested-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarXin Li (Intel) <xin@zytor.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250415175410.2944032-3-xin@zytor.com
parent 282cc5b6

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -476,7 +476,7 @@ 
#define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */

#define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */

#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */

#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */

arch/x86/include/asm/nospec-branch.h

+1 −1
Original line number Diff line number Diff line
@@ -327,7 +327,7 @@ 
.endm



.macro CLEAR_BRANCH_HISTORY_VMEXIT

	ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT

	ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_VMEXIT

.endm

#else

#define CLEAR_BRANCH_HISTORY

arch/x86/kernel/cpu/bugs.c

+3 −3
Original line number Diff line number Diff line
@@ -1701,13 +1701,13 @@ static void __init bhi_select_mitigation(void) 


	if (bhi_mitigation == BHI_MITIGATION_VMEXIT_ONLY) {

		pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit only\n");

		setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT);

		setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_VMEXIT);

		return;

	}



	pr_info("Spectre BHI mitigation: SW BHB clearing on syscall and VM exit\n");

	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP);

	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT);

	setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_VMEXIT);

}



static void __init spectre_v2_select_mitigation(void)
@@ -2891,7 +2891,7 @@ static const char *spectre_bhi_state(void) 
		 !boot_cpu_has(X86_FEATURE_RETPOLINE_LFENCE) &&

		 rrsba_disabled)

		return "; BHI: Retpoline";

	else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))

	else if (boot_cpu_has(X86_FEATURE_CLEAR_BHB_VMEXIT))

		return "; BHI: Vulnerable, KVM: SW loop";



	return "; BHI: Vulnerable";

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -466,7 +466,7 @@ 
#define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* Clear branch history at syscall entry using SW loop */

#define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */

#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_CLEAR_BHB_VMEXIT	(21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_AMD_FAST_CPPC	(21*32+ 5) /* Fast CPPC */

#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32+ 7) /* Workload Classification */