Commit 13fad66f authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Nuke intel_plane_config.tiling 



Use intel_fb_modifier_to_tiling() to convert the modifier into
the fence tiling mode during BIOS FB readout, rather than hand
rolling it. With this we can also stop tracking the tiling mode
in the intel_plane_config.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251107181126.5743-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 73206a75

drivers/gpu/drm/i915/display/i9xx_plane.c

+2 −4
Original line number Diff line number Diff line
@@ -1188,10 +1188,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
	val = intel_de_read(display, DSPCNTR(display, i9xx_plane));



	if (DISPLAY_VER(display) >= 4) {

		if (val & DISP_TILED) {

			plane_config->tiling = I915_TILING_X;

		if (val & DISP_TILED)

			fb->modifier = I915_FORMAT_MOD_X_TILED;

		}



		if (val & DISP_ROTATE_180)

			plane_config->rotation = DRM_MODE_ROTATE_180;
@@ -1211,7 +1209,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
				       DSPOFFSET(display, i9xx_plane));

		base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

	} else if (DISPLAY_VER(display) >= 4) {

		if (plane_config->tiling)

		if (fb->modifier == I915_FORMAT_MOD_X_TILED)

			offset = intel_de_read(display,

					       DSPTILEOFF(display, i9xx_plane));

		else

drivers/gpu/drm/i915/display/intel_display_types.h

+0 −1
Original line number Diff line number Diff line
@@ -726,7 +726,6 @@ struct intel_initial_plane_config { 
	struct intel_memory_region *mem;

	resource_size_t phys_base;

	struct i915_vma *vma;

	unsigned int tiling;

	int size;

	u32 base;

	u8 rotation;

drivers/gpu/drm/i915/display/intel_plane_initial.c

+7 −4
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ initial_plane_vma(struct intel_display *display, 
	struct drm_mm_node orig_mm = {};

	struct i915_vma *vma;

	resource_size_t phys_base;

	unsigned int tiling;

	u32 base, size;

	u64 pinctl;
@@ -179,17 +180,19 @@ initial_plane_vma(struct intel_display *display, 
	i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?

					    I915_CACHE_WT : I915_CACHE_NONE);



	switch (plane_config->tiling) {

	tiling = intel_fb_modifier_to_tiling(plane_config->fb->base.modifier);



	switch (tiling) {

	case I915_TILING_NONE:

		break;

	case I915_TILING_X:

	case I915_TILING_Y:

		obj->tiling_and_stride =

			plane_config->fb->base.pitches[0] |

			plane_config->tiling;

			tiling;

		break;

	default:

		MISSING_CASE(plane_config->tiling);

		MISSING_CASE(tiling);

		goto err_obj;

	}
@@ -374,7 +377,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, 
	plane_state->uapi.crtc_w = fb->width;

	plane_state->uapi.crtc_h = fb->height;



	if (plane_config->tiling)

	if (fb->modifier != DRM_FORMAT_MOD_LINEAR)

		dev_priv->preserve_bios_swizzle = true;



	plane_state->uapi.fb = fb;

drivers/gpu/drm/i915/display/skl_universal_plane.c

+0 −2
Original line number Diff line number Diff line
@@ -3090,11 +3090,9 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, 
		fb->modifier = DRM_FORMAT_MOD_LINEAR;

		break;

	case PLANE_CTL_TILED_X:

		plane_config->tiling = I915_TILING_X;

		fb->modifier = I915_FORMAT_MOD_X_TILED;

		break;

	case PLANE_CTL_TILED_Y:

		plane_config->tiling = I915_TILING_Y;

		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)

			if (DISPLAY_VER(display) >= 14)

				fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;