Commit 140f70ae authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/cdclk: update intel_dump_cdclk_config() logging 



Gather some intel_dump_cdclk_config() changes together to avoid extra
churn: Rename to intel_cdclk_dump_config() to following naming
conventions. Pass in i915. Use i915 for struct drm_device based
logging. Switch to KMS drm debug class.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/80469a83a74912ad69c4518d9cc68f07d65e9aaf.1642769982.git.jani.nikula@intel.com
parent 15d641c4

drivers/gpu/drm/i915/display/intel_cdclk.c

+11 −10
Original line number Diff line number Diff line
@@ -1156,7 +1156,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 
		goto sanitize;



	intel_update_cdclk(dev_priv);

	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");

	intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");



	/* Is PLL enabled and locked ? */

	if (dev_priv->cdclk.hw.vco == 0 ||
@@ -1817,7 +1817,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	int cdclk, clock, vco;



	intel_update_cdclk(dev_priv);

	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");

	intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");



	if (dev_priv->cdclk.hw.vco == 0 ||

	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
@@ -2057,10 +2057,11 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 
		a->voltage_level != b->voltage_level;

}



void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,

void intel_cdclk_dump_config(struct drm_i915_private *i915,

			     const struct intel_cdclk_config *cdclk_config,

			     const char *context)

{

	DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",

	drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",

		    context, cdclk_config->cdclk, cdclk_config->vco,

		    cdclk_config->ref, cdclk_config->bypass,

		    cdclk_config->voltage_level);
@@ -2087,7 +2088,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, 
	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))

		return;



	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");

	intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");



	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2130,8 +2131,8 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, 
	if (drm_WARN(&dev_priv->drm,

		     intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),

		     "cdclk state doesn't match!\n")) {

		intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");

		intel_dump_cdclk_config(cdclk_config, "[sw state]");

		intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");

		intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");

	}

}

drivers/gpu/drm/i915/display/intel_cdclk.h

+2 −1
Original line number Diff line number Diff line
@@ -62,7 +62,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 
			       const struct intel_cdclk_config *b);

void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);

void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);

void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,

void intel_cdclk_dump_config(struct drm_i915_private *i915,

			     const struct intel_cdclk_config *cdclk_config,

			     const char *context);

int intel_modeset_calc_cdclk(struct intel_atomic_state *state);

void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -9478,7 +9478,7 @@ void intel_modeset_init_hw(struct drm_i915_private *i915) 
	cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);



	intel_update_cdclk(i915);

	intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");

	intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");

	cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;

}

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -5580,7 +5580,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);



	intel_update_cdclk(dev_priv);

	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");

	intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");

}



/*