Commit 14128d64 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Replace several IS_METEORLAKE with proper IP version checks 



Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically.  Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.

v2:
 - Update two more conditions (one for pg_enable, one for MTL HuC
   compatibility).
v3:
 - Don't change GuC/HuC compatibility check, which sounds like it truly
   is specific to the MTL platform.  (Gustavo)
 - Drop a non-lineage workaround number for the OA timestamp frequency
   workaround.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-20-matthew.d.roper@intel.com
parent 2e3c369f

drivers/gpu/drm/i915/gem/i915_gem_create.c

+2 −2
Original line number Diff line number Diff line
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data) 
	BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=

		     offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));



	/* Limiting the extension only to Meteor Lake */

	if (!IS_METEORLAKE(i915))

	/* Limiting the extension only to Xe_LPG and beyond */

	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))

		return -ENODEV;



	if (copy_from_user(&ext, base, sizeof(ext)))

drivers/gpu/drm/i915/gt/intel_engine_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) 
{

	struct drm_i915_private *i915 = engine->i915;



	if (IS_METEORLAKE(i915) && engine->id == GSC0) {

	if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {

		intel_uncore_write(engine->gt->uncore,

				   RC_PSMI_CTRL_GSCCS,

				   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

drivers/gpu/drm/i915/gt/intel_mocs.c

+1 −1
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, 
	memset(table, 0, sizeof(struct drm_i915_mocs_table));



	table->unused_entries_index = I915_MOCS_PTE;

	if (IS_METEORLAKE(i915)) {

	if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {

		table->size = ARRAY_SIZE(mtl_mocs_table);

		table->table = mtl_mocs_table;

		table->n_entries = MTL_NUM_MOCS_ENTRIES;

drivers/gpu/drm/i915/gt/intel_rc6.c

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) 
	 * temporary wa and should be removed after fixing real cause

	 * of forcewake timeouts.

	 */

	if (IS_METEORLAKE(gt->i915))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))

		pg_enable =

			GEN9_MEDIA_PG_ENABLE |

			GEN11_MEDIA_SAMPLER_PG_ENABLE;

drivers/gpu/drm/i915/gt/intel_reset.c

+1 −1
Original line number Diff line number Diff line
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt) 


static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)

{

	if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))

	if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))

		return false;



	if (!__HAS_ENGINE(engine_mask, GSC0))