Commit 141af1be authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source 



The clk_dp_ops are supposed to be used for DP-related clocks with a
proper MND divier. Use standard RCG2 ops for dptx1_aux_clk_src, the same
as all other DPTX AUX clocks in this driver.

Fixes: 16fb89f9 ("clk: qcom: Add support for Display Clock Controller on SM8450")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260112-dp-aux-clks-v1-2-456b0c11b069@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 6de23f81

drivers/clk/qcom/dispcc-sm8450.c

+1 −1
Original line number Diff line number Diff line
@@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 
		.parent_data = disp_cc_parent_data_1,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_dp_ops,

		.ops = &clk_rcg2_ops,

	},

};