Commit 14449382 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-cpufreq' 

Merge cpufreq updates for 6.10:

 - Rework the handling of disabled turbo in the intel_pstate driver and
   make it update the maximum CPU frequency consistently regardless of
   the reason on top of a number of cleanups (Rafael Wysocki).

 - Add missing checks for NULL .exit() cpufreq driver callback to the
   cpufreq core (Viresh Kumar).

 - Prevent pulicy->max from going above the frequency QoS maximum value
   when cpufreq_frequency_table_verify() is used (Xuewen Yan).

 - Prevent a negative CPU number or frequency value from being printed
   if they are really large (Joshua Yeong).

 - Update MAINTAINERS entry for amd-pstate to add two new submaintainers
   and a designated reviewer (Huang Rui).

 - Clean up the amd-pstate driver and update its documentation (Gautham
   Shenoy).

 - Fix the highest frequency issue in the amd-pstate driver which limits
   performance (Perry Yuan).

 - Enable CPPC v2 for certain processors in the family 17H, as requested
   by TR40 processor users who expect improved performance and lower
   system temperature (Perry Yuan).

 - Change latency and delay values to be read from platform firmware
   firstly for more accurate timing (Perry Yuan).

 - A new quirk is introduced for supporting amd-pstate on legacy
   processors which either lack CPPC capability, or only only have CPPC
   v2 capability (Perry Yuan).

 - Sun50i: Add support for opp_supported_hw, H616 platform and general
   cleanups (Andre Przywara, Martin Botka, Brandon Cheo Fusi, Dan
   Carpenter, Viresh Kumar).

 - CPPC: Fix possible null pointer dereference (Aleksandr Mishin).

 - Eliminate uses of of_node_put() (Javier Carrasco, and Shivani Gupta).

 - brcmstb-avs: ISO C90 forbids mixed declarations (Portia Stephens).

 - mediatek: Add support for MT7988A (Sam Shih).

 - cpufreq-qcom-hw: Add SM4450 compatibles in DT bindings (Tengfei Fan).

 - Fix struct cpudata::epp_cached kernel-doc in the intel_pstate cpufreq
   driver (Jeff Johnson).

* pm-cpufreq: (46 commits)
  cpufreq: amd-pstate: fix the highest frequency issue which limits performance
  cpufreq: intel_pstate: fix struct cpudata::epp_cached kernel-doc
  cpufreq: Fix up printing large CPU numbers and frequency values
  MAINTAINERS: cpufreq: amd-pstate: Add co-maintainers and reviewer
  cpufreq: amd-pstate: remove unused variable lowest_nonlinear_freq
  cpufreq: amd-pstate: fix code format problems
  cpufreq: amd-pstate: Add quirk for the pstate CPPC capabilities missing
  cppc_acpi: print error message if CPPC is unsupported
  cpufreq: amd-pstate: get transition delay and latency value from ACPI tables
  cpufreq: amd-pstate: Bail out if min/max/nominal_freq is 0
  cpufreq: amd-pstate: Remove amd_get_{min,max,nominal,lowest_nonlinear}_freq()
  cpufreq: amd-pstate: Unify computation of {max,min,nominal,lowest_nonlinear}_freq
  cpufreq: amd-pstate: Document the units for freq variables in amd_cpudata
  cpufreq: amd-pstate: Document *_limit_* fields in struct amd_cpudata
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles
  cpufreq: sun50i: fix error returns in dt_has_supported_hw()
  cpufreq: brcmstb-avs-cpufreq: ISO C90 forbids mixed declarations
  cpufreq: dt-platdev: eliminate uses of of_node_put()
  cpufreq: dt: eliminate uses of of_node_put()
  cpufreq: ti: Implement scope-based cleanup in ti_cpufreq_match_node()
  ...
parents eefb5dbd bf202e65

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

+2 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ properties: 
              - qcom,sc7280-cpufreq-epss

              - qcom,sc8280xp-cpufreq-epss

              - qcom,sdx75-cpufreq-epss

              - qcom,sm4450-cpufreq-epss

              - qcom,sm6375-cpufreq-epss

              - qcom,sm8250-cpufreq-epss

              - qcom,sm8350-cpufreq-epss
@@ -133,6 +134,7 @@ allOf: 
              - qcom,sc8280xp-cpufreq-epss

              - qcom,sdm670-cpufreq-hw

              - qcom,sdm845-cpufreq-hw

              - qcom,sm4450-cpufreq-epss

              - qcom,sm6115-cpufreq-hw

              - qcom,sm6350-cpufreq-hw

              - qcom,sm6375-cpufreq-epss

Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml

+43 −44
Original line number Diff line number Diff line
@@ -13,25 +13,25 @@ maintainers: 
description: |

  For some SoCs, the CPU frequency subset and voltage value of each

  OPP varies based on the silicon variant in use. Allwinner Process

  Voltage Scaling Tables defines the voltage and frequency value based

  on the speedbin blown in the efuse combination. The

  sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to

  provide the OPP framework with required information.

  Voltage Scaling Tables define the voltage and frequency values based

  on the speedbin blown in the efuse combination.



allOf:

  - $ref: opp-v2-base.yaml#



properties:

  compatible:

    const: allwinner,sun50i-h6-operating-points

    enum:

      - allwinner,sun50i-h6-operating-points

      - allwinner,sun50i-h616-operating-points



  nvmem-cells:

    description: |

      A phandle pointing to a nvmem-cells node representing the efuse

      registers that has information about the speedbin that is used

      register that has information about the speedbin that is used

      to select the right frequency/voltage value pair. Please refer

      the for nvmem-cells bindings

      Documentation/devicetree/bindings/nvmem/nvmem.txt and also

      to the nvmem-cells bindings in

      Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the

      examples below.



  opp-shared: true
@@ -47,15 +47,18 @@ patternProperties: 
    properties:

      opp-hz: true

      clock-latency-ns: true

      opp-microvolt: true

      opp-supported-hw:

        maxItems: 1

        description:

          A single 32 bit bitmap value, representing compatible HW, one

          bit per speed bin index.



    patternProperties:

      "^opp-microvolt-speed[0-9]$": true



    required:

      - opp-hz

      - opp-microvolt-speed0

      - opp-microvolt-speed1

      - opp-microvolt-speed2



    unevaluatedProperties: false
@@ -77,58 +80,54 @@ examples: 
            opp-microvolt-speed2 = <800000>;

        };



        opp-720000000 {

        opp-1080000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <720000000>;

            opp-hz = /bits/ 64 <1080000000>;



            opp-microvolt-speed0 = <880000>;

            opp-microvolt-speed1 = <820000>;

            opp-microvolt-speed2 = <800000>;

            opp-microvolt-speed0 = <1060000>;

            opp-microvolt-speed1 = <880000>;

            opp-microvolt-speed2 = <840000>;

        };



        opp-816000000 {

        opp-1488000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <816000000>;

            opp-hz = /bits/ 64 <1488000000>;



            opp-microvolt-speed0 = <880000>;

            opp-microvolt-speed1 = <820000>;

            opp-microvolt-speed2 = <800000>;

            opp-microvolt-speed0 = <1160000>;

            opp-microvolt-speed1 = <1000000>;

            opp-microvolt-speed2 = <960000>;

        };



        opp-888000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <888000000>;



            opp-microvolt-speed0 = <940000>;

            opp-microvolt-speed1 = <820000>;

            opp-microvolt-speed2 = <800000>;

    };



        opp-1080000000 {

  - |

    opp-table {

        compatible = "allwinner,sun50i-h616-operating-points";

        nvmem-cells = <&speedbin_efuse>;

        opp-shared;



        opp-480000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <1080000000>;

            opp-hz = /bits/ 64 <480000000>;



            opp-microvolt-speed0 = <1060000>;

            opp-microvolt-speed1 = <880000>;

            opp-microvolt-speed2 = <840000>;

            opp-microvolt = <900000>;

            opp-supported-hw = <0x1f>;

        };



        opp-1320000000 {

        opp-792000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <1320000000>;

            opp-hz = /bits/ 64 <792000000>;



            opp-microvolt-speed0 = <1160000>;

            opp-microvolt-speed1 = <940000>;

            opp-microvolt-speed2 = <900000>;

            opp-microvolt-speed1 = <900000>;

            opp-microvolt-speed4 = <940000>;

            opp-supported-hw = <0x12>;

        };



        opp-1488000000 {

        opp-1512000000 {

            clock-latency-ns = <244144>; /* 8 32k periods */

            opp-hz = /bits/ 64 <1488000000>;

            opp-hz = /bits/ 64 <1512000000>;



            opp-microvolt-speed0 = <1160000>;

            opp-microvolt-speed1 = <1000000>;

            opp-microvolt-speed2 = <960000>;

            opp-microvolt = <1100000>;

            opp-supported-hw = <0x0a>;

        };

    };

MAINTAINERS

+3 −0
Original line number Diff line number Diff line
@@ -1062,6 +1062,9 @@ F: drivers/gpu/drm/amd/pm/ 








AMD PSTATE DRIVER









M:	Huang Rui <ray.huang@amd.com>









M:	Gautham R. Shenoy <gautham.shenoy@amd.com>









M:	Mario Limonciello <mario.limonciello@amd.com>









R:	Perry Yuan <perry.yuan@amd.com>









L:	linux-pm@vger.kernel.org









S:	Supported









F:	Documentation/admin-guide/pm/amd-pstate.rst
































arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi



+5
−0






























Original line number
Diff line number
Diff line







@@ -6,6 +6,7 @@







/dts-v1/;



















#include "sun50i-h616.dtsi"









#include "sun50i-h616-cpu-opp.dtsi"



















#include <dt-bindings/gpio/gpio.h>









#include <dt-bindings/interrupt-controller/arm-gic.h>








@@ -62,6 +63,10 @@ wifi_pwrseq: wifi-pwrseq {







	};









};



















&cpu0 {









	cpu-supply = <&reg_dcdc2>;









};



















&mmc0 {









	vmmc-supply = <&reg_dldo1>;









	/* Card detection pin is not connected */
































arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
0 → 100644



+115
−0






























Original line number
Diff line number
Diff line









// SPDX-License-Identifier: (GPL-2.0+ OR MIT)









// Copyright (C) 2023 Martin Botka <martin@somainline.org>



















/ {









	cpu_opp_table: opp-table-cpu {









		compatible = "allwinner,sun50i-h616-operating-points";









		nvmem-cells = <&cpu_speed_grade>;









		opp-shared;



















		opp-480000000 {









			opp-hz = /bits/ 64 <480000000>;









			opp-microvolt = <900000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x1f>;









		};



















		opp-600000000 {









			opp-hz = /bits/ 64 <600000000>;









			opp-microvolt = <900000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x12>;









		};



















		opp-720000000 {









			opp-hz = /bits/ 64 <720000000>;









			opp-microvolt = <900000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x0d>;









		};



















		opp-792000000 {









			opp-hz = /bits/ 64 <792000000>;









			opp-microvolt-speed1 = <900000>;









			opp-microvolt-speed4 = <940000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x12>;









		};



















		opp-936000000 {









			opp-hz = /bits/ 64 <936000000>;









			opp-microvolt = <900000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x0d>;









		};



















		opp-1008000000 {









			opp-hz = /bits/ 64 <1008000000>;









			opp-microvolt-speed0 = <950000>;









			opp-microvolt-speed1 = <940000>;









			opp-microvolt-speed2 = <950000>;









			opp-microvolt-speed3 = <950000>;









			opp-microvolt-speed4 = <1020000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x1f>;









		};



















		opp-1104000000 {









			opp-hz = /bits/ 64 <1104000000>;









			opp-microvolt-speed0 = <1000000>;









			opp-microvolt-speed2 = <1000000>;









			opp-microvolt-speed3 = <1000000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x0d>;









		};



















		opp-1200000000 {









			opp-hz = /bits/ 64 <1200000000>;









			opp-microvolt-speed0 = <1050000>;









			opp-microvolt-speed1 = <1020000>;









			opp-microvolt-speed2 = <1050000>;









			opp-microvolt-speed3 = <1050000>;









			opp-microvolt-speed4 = <1100000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x1f>;









		};



















		opp-1320000000 {









			opp-hz = /bits/ 64 <1320000000>;









			opp-microvolt = <1100000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x1d>;









		};



















		opp-1416000000 {









			opp-hz = /bits/ 64 <1416000000>;









			opp-microvolt = <1100000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x0d>;









		};



















		opp-1512000000 {









			opp-hz = /bits/ 64 <1512000000>;









			opp-microvolt-speed1 = <1100000>;









			opp-microvolt-speed3 = <1100000>;









			clock-latency-ns = <244144>; /* 8 32k periods */









			opp-supported-hw = <0x0a>;









		};









	};









};



















&cpu0 {









	operating-points-v2 = <&cpu_opp_table>;









};



















&cpu1 {









	operating-points-v2 = <&cpu_opp_table>;









};



















&cpu2 {









	operating-points-v2 = <&cpu_opp_table>;









};



















&cpu3 {









	operating-points-v2 = <&cpu_opp_table>;









};