Commit 14656c4f authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Allow Z8 for multiplane configurations on DCN35 



[Why]
Power improvement over DCN314, but also addresses a functional issue
where plane_state remains uncleared on pipes that aren't actually
active.

[How]
Update the check to allow for zero streams to be treated as z8 allow.
Update the check to remove plane count on the active stream case.

Z8 will still be blocked based on stutter duration, which is likely to
be the case for most multi plane configurations.

Reviewed-by: default avatarGabe Teeger <gabe.teeger@amd.com>
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aa4e18d3

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

+2 −2
Original line number Diff line number Diff line
@@ -583,9 +583,9 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context) 
			plane_count++;

	}



	if (plane_count == 0) {

	if (context->stream_count == 0 || plane_count == 0) {

		support = DCN_ZSTATE_SUPPORT_ALLOW;

	} else if (plane_count == 1 && context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {

	} else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {

		struct dc_link *link = context->streams[0]->sink->link;

		bool is_pwrseq0 = link && link->link_index == 0;

		bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;