Commit 14a1e6a4 authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe: Clarify number of dwords/qwords stored by MI_STORE_DATA_IMM 



MI_STORE_DATA_IMM can store either dword values or qword values, and can
store more than one value if the instruction's length field is large
enough.  Create explicit defines to specify the number of dwords/qwords
to be stored, which will set the instruction length correctly and, if
necessary, turn on the 'store qword' bit.

While we're here, also replace an open-coded version of
MI_STORE_DATA_IMM with the common macros.

Bspec: 60246
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-11-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent e12a6488

drivers/gpu/drm/xe/regs/xe_gpu_commands.h

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ 


#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)

#define MI_STORE_DATA_IMM	MI_INSTR(0x20, 0)

#define   MI_SDI_GGTT		REG_BIT(22)

#define   MI_SDI_NUM_DW(x)	((x) + 1)

#define   MI_SDI_NUM_QW(x)	(REG_BIT(21) | (2 * (x) + 1))



#define MI_LOAD_REGISTER_IMM	MI_INSTR(0x22, 0)

#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)

drivers/gpu/drm/xe/xe_migrate.c

+3 −6
Original line number Diff line number Diff line
@@ -482,8 +482,7 @@ static void emit_pte(struct xe_migrate *m, 
	while (ptes) {

		u32 chunk = min(0x1ffU, ptes);



		bb->cs[bb->len++] = MI_STORE_DATA_IMM | BIT(21) |

			(chunk * 2 + 1);

		bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);

		bb->cs[bb->len++] = ofs;

		bb->cs[bb->len++] = 0;
@@ -1083,8 +1082,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs, 
		if (!(bb->len & 1))

			bb->cs[bb->len++] = MI_NOOP;



		bb->cs[bb->len++] = MI_STORE_DATA_IMM | BIT(21) |

			(chunk * 2 + 1);

		bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);

		bb->cs[bb->len++] = lower_32_bits(addr);

		bb->cs[bb->len++] = upper_32_bits(addr);

		ops->populate(pt_update, tile, NULL, bb->cs + bb->len, ofs, chunk,
@@ -1290,8 +1288,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, 
		emit_arb_clear(bb);



		/* Map our PT's to gtt */

		bb->cs[bb->len++] = MI_STORE_DATA_IMM | BIT(21) |

			(num_updates * 2 + 1);

		bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(num_updates);

		bb->cs[bb->len++] = ppgtt_ofs * XE_PAGE_SIZE + page_ofs;

		bb->cs[bb->len++] = 0; /* upper_32_bits */

drivers/gpu/drm/xe/xe_ring_ops.c

+2 −4
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static int emit_user_interrupt(u32 *dw, int i) 


static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)

{

	dw[i++] = MI_STORE_DATA_IMM | BIT(22) /* GGTT */ | 2;

	dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);

	dw[i++] = addr;

	dw[i++] = 0;

	dw[i++] = value;
@@ -140,12 +140,10 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw, 
	return i;

}



#define MI_STORE_QWORD_IMM_GEN8_POSTED (MI_INSTR(0x20, 3) | (1 << 21))



static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,

				       u32 *dw, int i)

{

	dw[i++] = MI_STORE_QWORD_IMM_GEN8_POSTED;

	dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);

	dw[i++] = lower_32_bits(addr);

	dw[i++] = upper_32_bits(addr);

	dw[i++] = lower_32_bits(value);