Unverified Commit 14b15aeb authored by Jim Quinlan's avatar Jim Quinlan Committed by Krzysztof Wilczyński
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dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" 

The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
requires the driver to deliberately place the RC HW one of three CLKREQ#
modes.  The "brcm,clkreq-mode" property allows the user to override the
default setting.  If this property is omitted, the default mode shall be
"default".

Link: https://lore.kernel.org/linux-pci/20231113185607.1756-2-james.quinlan@broadcom.com


Tested-by: default avatarCyril Brulebois <cyril@debamax.com>
Tested-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarJim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent b85ea95d

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

+18 −0
Original line number Diff line number Diff line
@@ -64,6 +64,24 @@ properties: 


  aspm-no-l0s: true



  brcm,clkreq-mode:

    description: A string that determines the operating

      clkreq mode of the PCIe RC HW with respect to controlling the refclk

      signal.  There are three different modes -- "safe", which drives the

      refclk signal unconditionally and will work for all devices but does

      not provide any power savings; "no-l1ss" -- which provides Clock

      Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)

      power savings. If the downstream device connected to the RC is L1SS

      capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,

      potentially hanging the system; "default" -- which provides L0s, L1,

      and L1SS, but not compliant to provide Clock Power Management;

      specifically, may not be able to meet the T_CLRon max timing of 400ns

      as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI

      Express Mini CEM 2.1 specification.  This situation is atypical and

      should happen only with older devices.

    $ref: /schemas/types.yaml#/definitions/string

    enum: [ safe, no-l1ss, default ]



  brcm,scb-sizes:

    description: u64 giving the 64bit PCIe memory

      viewport size of a memory controller.  There may be up to