Commit 14b6e9f4 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

wifi: rtw89: 8852b: implement chip_ops::{enable,disable}_bb_rf 



Implement to power on/off BB and RF via MAC registers.

Add return type of chip_ops::disable_bb_rf, because it could fail to
disable. Also, correct naming of register 0x0200 used by the ops as well.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-5-pkshih@realtek.com
parent 61bdf7aa

drivers/net/wireless/realtek/rtw89/core.c

+3 −1
Original line number Diff line number Diff line
@@ -2949,7 +2949,9 @@ int rtw89_core_start(struct rtw89_dev *rtwdev) 
	/* efuse process */



	/* pre-config BB/RF, BB reset/RFC reset */

	rtw89_chip_disable_bb_rf(rtwdev);

	ret = rtw89_chip_disable_bb_rf(rtwdev);

	if (ret)

		return ret;

	ret = rtw89_chip_enable_bb_rf(rtwdev);

	if (ret)

		return ret;

drivers/net/wireless/realtek/rtw89/core.h

+1 −1
Original line number Diff line number Diff line
@@ -2292,7 +2292,7 @@ struct rtw89_hci_info { 


struct rtw89_chip_ops {

	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);

	void (*disable_bb_rf)(struct rtw89_dev *rtwdev);

	int (*disable_bb_rf)(struct rtw89_dev *rtwdev);

	void (*bb_reset)(struct rtw89_dev *rtwdev,

			 enum rtw89_phy_idx phy_idx);

	void (*bb_sethw)(struct rtw89_dev *rtwdev);

drivers/net/wireless/realtek/rtw89/mac.c

+5 −3
Original line number Diff line number Diff line
@@ -1224,8 +1224,8 @@ static int chip_func_en(struct rtw89_dev *rtwdev) 
{

	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;



	if (chip_id == RTL8852A)

		rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0,

	if (chip_id == RTL8852A || chip_id == RTL8852B)

		rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,

				  B_AX_OCP_L1_MASK);



	return 0;
@@ -3205,7 +3205,7 @@ int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 
}

EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);



void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)

int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)

{

	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,

			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
@@ -3213,6 +3213,8 @@ void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 
			  B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |

			  B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);

	rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);



	return 0;

}

EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);

drivers/net/wireless/realtek/rtw89/mac.h

+5 −3
Original line number Diff line number Diff line
@@ -805,7 +805,7 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 
					struct ieee80211_vif *vif);

int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);

int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);

void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);

int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);



static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)

{
@@ -814,11 +814,11 @@ static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 
	return chip->ops->enable_bb_rf(rtwdev);

}



static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)

static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)

{

	const struct rtw89_chip_info *chip = rtwdev->chip;



	chip->ops->disable_bb_rf(rtwdev);

	return chip->ops->disable_bb_rf(rtwdev);

}



u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
@@ -988,8 +988,10 @@ enum rtw89_mac_xtal_si_offset { 
#define XTAL_SI_HIGH_ADDR_MASK	GENMASK(2, 0)

	XTAL_SI_READ_VAL = 0x7A,

	XTAL_SI_WL_RFC_S0 = 0x80,

#define XTAL_SI_RF00S_EN	GENMASK(2, 0)

#define XTAL_SI_RF00		BIT(0)

	XTAL_SI_WL_RFC_S1 = 0x81,

#define XTAL_SI_RF10S_EN	GENMASK(2, 0)

#define XTAL_SI_RF10		BIT(0)

	XTAL_SI_ANAPAR_WL = 0x90,

#define XTAL_SI_SRAM2RFC	BIT(7)

drivers/net/wireless/realtek/rtw89/reg.h

+7 −3
Original line number Diff line number Diff line
@@ -51,9 +51,6 @@ 
#define B_AX_EF_POR BIT(10)

#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)



#define R_AX_SPSLDO_ON_CTRL0 0x0200

#define B_AX_OCP_L1_MASK GENMASK(15, 13)



#define R_AX_EFUSE_CTRL 0x0030

#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)

#define B_AX_EF_RDY BIT(29)
@@ -203,6 +200,12 @@ 
#define R_AX_UDM2 0x01F8

#define R_AX_UDM3 0x01FC



#define R_AX_SPS_DIG_ON_CTRL0 0x0200

#define B_AX_VREFPFM_L_MASK GENMASK(25, 22)

#define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)

#define B_AX_OCP_L1_MASK GENMASK(15, 13)

#define B_AX_VOL_L1_MASK GENMASK(3, 0)



#define R_AX_LDO_AON_CTRL0 0x0218

#define B_AX_PD_REGU_L BIT(16)
@@ -395,6 +398,7 @@ 


#define R_AX_PHYREG_SET 0x8040

#define PHYREG_SET_ALL_CYCLE 0x8

#define PHYREG_SET_XYN_CYCLE 0xE



#define R_AX_HD0IMR 0x8110

#define B_AX_WDT_PTFM_INT_EN BIT(5)