Commit 150f8815 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'intel/drm-intel-fixes' of /ssd/git/drm-next into drm-fixes 

* 'intel/drm-intel-fixes' of /ssd/git/drm-next:
  Revert "drm/i915/dp: use VBT provided eDP params if available"
  drm/i915: Clear pfit registers when not used by any outputs
  drm/i915: fix regression due to ba3d8d74
parents c5027dec 3cf2efb1

drivers/gpu/drm/i915/i915_gem.c

+18 −25
Original line number Diff line number Diff line
@@ -38,8 +38,7 @@ 


static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);



static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,

						  bool pipelined);

static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);

static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);

static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);

static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
@@ -2594,7 +2593,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj, 
	if (reg->gpu) {

		int ret;



		ret = i915_gem_object_flush_gpu_write_domain(obj, true);

		ret = i915_gem_object_flush_gpu_write_domain(obj);

		if (ret)

			return ret;
@@ -2742,8 +2741,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj) 


/** Flushes any GPU write domain for the object if it's dirty. */

static int

i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,

				       bool pipelined)

i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)

{

	struct drm_device *dev = obj->dev;

	uint32_t old_write_domain;
@@ -2762,10 +2760,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, 
					    obj->read_domains,

					    old_write_domain);



	if (pipelined)

	return 0;



	return i915_gem_object_wait_rendering(obj, true);

}



/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2826,17 +2821,14 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) 
	if (obj_priv->gtt_space == NULL)

		return -EINVAL;



	ret = i915_gem_object_flush_gpu_write_domain(obj, false);

	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret != 0)

		return ret;



	i915_gem_object_flush_cpu_write_domain(obj);



	if (write) {

	ret = i915_gem_object_wait_rendering(obj, true);

	if (ret)

		return ret;

	}



	i915_gem_object_flush_cpu_write_domain(obj);



	old_write_domain = obj->write_domain;

	old_read_domains = obj->read_domains;
@@ -2875,7 +2867,7 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, 
	if (obj_priv->gtt_space == NULL)

		return -EINVAL;



	ret = i915_gem_object_flush_gpu_write_domain(obj, true);

	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret)

		return ret;
@@ -2924,9 +2916,12 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) 
	uint32_t old_write_domain, old_read_domains;

	int ret;



	ret = i915_gem_object_flush_gpu_write_domain(obj, false);

	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret != 0)

		return ret;

	ret = i915_gem_object_wait_rendering(obj, true);

	if (ret)

		return ret;



	i915_gem_object_flush_gtt_write_domain(obj);
@@ -2935,12 +2930,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) 
	 */

	i915_gem_object_set_to_full_cpu_read_domain(obj);



	if (write) {

		ret = i915_gem_object_wait_rendering(obj, true);

		if (ret)

			return ret;

	}



	old_write_domain = obj->write_domain;

	old_read_domains = obj->read_domains;
@@ -3205,9 +3194,13 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, 
	if (offset == 0 && size == obj->size)

		return i915_gem_object_set_to_cpu_domain(obj, 0);



	ret = i915_gem_object_flush_gpu_write_domain(obj, false);

	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret != 0)

		return ret;

	ret = i915_gem_object_wait_rendering(obj, true);

	if (ret)

		return ret;



	i915_gem_object_flush_gtt_write_domain(obj);



	/* If we're already fully in the CPU read domain, we're done. */

drivers/gpu/drm/i915/intel_display.c

+6 −1
Original line number Diff line number Diff line
@@ -5336,9 +5336,14 @@ static void intel_setup_outputs(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_encoder *encoder;

	bool dpd_is_edp = false;

	bool has_lvds = false;



	if (IS_MOBILE(dev) && !IS_I830(dev))

		intel_lvds_init(dev);

		has_lvds = intel_lvds_init(dev);

	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {

		/* disable the panel fitter on everything but LVDS */

		I915_WRITE(PFIT_CONTROL, 0);

	}



	if (HAS_PCH_SPLIT(dev)) {

		dpd_is_edp = intel_dpd_is_edp(dev);

drivers/gpu/drm/i915/intel_dp.c

+57 −89
Original line number Diff line number Diff line
@@ -584,17 +584,6 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
		mode->clock = dev_priv->panel_fixed_mode->clock;

	}



	/* Just use VBT values for eDP */

	if (is_edp(intel_dp)) {

		intel_dp->lane_count = dev_priv->edp.lanes;

		intel_dp->link_bw = dev_priv->edp.rate;

		adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);

		DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",

			      intel_dp->link_bw, intel_dp->lane_count,

			      adjusted_mode->clock);

		return true;

	}



	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {

		for (clock = 0; clock <= max_clock; clock++) {

			int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
@@ -613,6 +602,19 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 
		}

	}



	if (is_edp(intel_dp)) {

		/* okay we failed just pick the highest */

		intel_dp->lane_count = max_lane_count;

		intel_dp->link_bw = bws[max_clock];

		adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);

		DRM_DEBUG_KMS("Force picking display port link bw %02x lane "

			      "count %d clock %d\n",

			      intel_dp->link_bw, intel_dp->lane_count,

			      adjusted_mode->clock);



		return true;

	}



	return false;

}
@@ -1087,21 +1089,11 @@ intel_get_adjust_train(struct intel_dp *intel_dp) 
}



static uint32_t

intel_dp_signal_levels(struct intel_dp *intel_dp)

intel_dp_signal_levels(uint8_t train_set, int lane_count)

{

	struct drm_device *dev = intel_dp->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t	signal_levels = 0;

	u8 train_set = intel_dp->train_set[0];

	u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;

	u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;



	if (is_edp(intel_dp)) {

		vswing = dev_priv->edp.vswing;

		preemphasis = dev_priv->edp.preemphasis;

	}



	switch (vswing) {

	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {

	case DP_TRAIN_VOLTAGE_SWING_400:

	default:

		signal_levels |= DP_VOLTAGE_0_4;
@@ -1116,7 +1108,7 @@ intel_dp_signal_levels(struct intel_dp *intel_dp) 
		signal_levels |= DP_VOLTAGE_1_2;

		break;

	}

	switch (preemphasis) {

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {

	case DP_TRAIN_PRE_EMPHASIS_0:

	default:

		signal_levels |= DP_PRE_EMPHASIS_0;
@@ -1202,18 +1194,6 @@ intel_channel_eq_ok(struct intel_dp *intel_dp) 
	return true;

}



static bool

intel_dp_aux_handshake_required(struct intel_dp *intel_dp)

{

	struct drm_device *dev = intel_dp->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (is_edp(intel_dp) && dev_priv->no_aux_handshake)

		return false;



	return true;

}



static bool

intel_dp_set_link_train(struct intel_dp *intel_dp,

			uint32_t dp_reg_value,
@@ -1226,9 +1206,6 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, 
	I915_WRITE(intel_dp->output_reg, dp_reg_value);

	POSTING_READ(intel_dp->output_reg);



	if (!intel_dp_aux_handshake_required(intel_dp))

		return true;



	intel_dp_aux_native_write_1(intel_dp,

				    DP_TRAINING_PATTERN_SET,

				    dp_train_pat);
@@ -1261,7 +1238,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
	POSTING_READ(intel_dp->output_reg);

	intel_wait_for_vblank(dev, intel_crtc->pipe);



	if (intel_dp_aux_handshake_required(intel_dp))

	/* Write the link configuration data */

	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,

				  intel_dp->link_configuration,
@@ -1283,7 +1259,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);

			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;

		} else {

			signal_levels = intel_dp_signal_levels(intel_dp);

			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);

			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;

		}
@@ -1297,10 +1273,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
			break;

		/* Set training pattern 1 */



		udelay(500);

		if (intel_dp_aux_handshake_required(intel_dp)) {

			break;

		} else {

		udelay(100);

		if (!intel_dp_get_link_status(intel_dp))

			break;
@@ -1328,7 +1301,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
		/* Compute new intel_dp->train_set as requested by target */

		intel_get_adjust_train(intel_dp);

	}

	}



	intel_dp->DP = DP;

}
@@ -1354,7 +1326,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) 
			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);

			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;

		} else {

			signal_levels = intel_dp_signal_levels(intel_dp);

			signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);

			DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;

		}
@@ -1368,11 +1340,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) 
					     DP_TRAINING_PATTERN_2))

			break;



		udelay(500);



		if (!intel_dp_aux_handshake_required(intel_dp)) {

			break;

		} else {

		udelay(400);

		if (!intel_dp_get_link_status(intel_dp))

			break;
@@ -1389,7 +1357,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) 
		intel_get_adjust_train(intel_dp);

		++tries;

	}

	}



	if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))

		reg = DP | DP_LINK_TRAIN_OFF_CPT;

	else

drivers/gpu/drm/i915/intel_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ extern bool intel_sdvo_init(struct drm_device *dev, int output_device); 
extern void intel_dvo_init(struct drm_device *dev);

extern void intel_tv_init(struct drm_device *dev);

extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj);

extern void intel_lvds_init(struct drm_device *dev);

extern bool intel_lvds_init(struct drm_device *dev);

extern void intel_dp_init(struct drm_device *dev, int dp_reg);

void

intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,

drivers/gpu/drm/i915/intel_lvds.c

+10 −9
Original line number Diff line number Diff line
@@ -837,7 +837,7 @@ static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin) 
 * Create the connector, register the LVDS DDC bus, and try to figure out what

 * modes we can display on the LVDS panel (if present).

 */

void intel_lvds_init(struct drm_device *dev)

bool intel_lvds_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_lvds *intel_lvds;
@@ -853,37 +853,37 @@ void intel_lvds_init(struct drm_device *dev) 


	/* Skip init on machines we know falsely report LVDS */

	if (dmi_check_system(intel_no_lvds))

		return;

		return false;



	pin = GMBUS_PORT_PANEL;

	if (!lvds_is_present_in_vbt(dev, &pin)) {

		DRM_DEBUG_KMS("LVDS is not present in VBT\n");

		return;

		return false;

	}



	if (HAS_PCH_SPLIT(dev)) {

		if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)

			return;

			return false;

		if (dev_priv->edp.support) {

			DRM_DEBUG_KMS("disable LVDS for eDP support\n");

			return;

			return false;

		}

	}



	if (!intel_lvds_ddc_probe(dev, pin)) {

		DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n");

		return;

		return false;

	}



	intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);

	if (!intel_lvds) {

		return;

		return false;

	}



	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);

	if (!intel_connector) {

		kfree(intel_lvds);

		return;

		return false;

	}



	if (!HAS_PCH_SPLIT(dev)) {
@@ -1026,7 +1026,7 @@ void intel_lvds_init(struct drm_device *dev) 
	/* keep the LVDS connector */

	dev_priv->int_lvds_connector = connector;

	drm_sysfs_connector_add(connector);

	return;

	return true;



failed:

	DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
@@ -1034,4 +1034,5 @@ void intel_lvds_init(struct drm_device *dev) 
	drm_encoder_cleanup(encoder);

	kfree(intel_lvds);

	kfree(intel_connector);

	return false;

}