Unverified Commit 154a3706 authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zacas ISA extension 



Export Zacas ISA extension through hwprobe.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231220155723.684081-6-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 188a2122

Documentation/arch/riscv/hwprobe.rst

+4 −0
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@@ -165,6 +165,10 @@ The following keys are defined: 
       defined in the RISC-V ISA manual starting from commit 5618fb5a216b

       ("Ztso is now ratified.")



  * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as

       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting

       from commit 5059e0ca641c ("update to ratified").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
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@@ -57,6 +57,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)

#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)

#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)

#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_riscv.c

+1 −0
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@@ -175,6 +175,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZKT);

		EXT_KEY(ZIHINTNTL);

		EXT_KEY(ZTSO);

		EXT_KEY(ZACAS);



		if (has_vector()) {

			EXT_KEY(ZVBB);