Commit 15b1d7b7 authored Jan 13, 2026 by Zhongwei Committed by Alex Deucher Jan 27, 2026

drm/amd/display: avoid dig reg access timeout on usb4 link training fail



[Why]
When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK
source should be changed back to phy clock. In enable_streams, it is
assumed that link training succeeded and will switch from refclk to
phy clock. But phy clk here might not be on. Dig reg access timeout
will occur.

[How]
When enable_stream is hit, check if link training failed for usb4.
If it did, fall back to the ref clock to avoid reg access timeout.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent c37084e2

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -3058,10 +3058,18 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
		dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
		}
		} else {
		if (dccg->funcs->enable_symclk_se)
		if (dccg->funcs->enable_symclk_se && link_enc) {
		if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA
		&& link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN
		&& !link->link_status.link_active) {
		if (dccg->funcs->disable_symclk_se)
		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
		link_enc->transmitter - TRANSMITTER_UNIPHY_A);
		} else
		dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
		link_enc->transmitter - TRANSMITTER_UNIPHY_A);
		}
		}

		if (dc->res_pool->dccg->funcs->set_pixel_rate_div)
		dc->res_pool->dccg->funcs->set_pixel_rate_div(