Commit 160d7b9f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-stm', 'clk-cleanup', 'clk-kunit' and 'clk-mediatek' into clk-next 

 - Add reset support to Airoha EN7581 clk driver
 - Add module description to mediatek clk drivers

* clk-stm:
  clk: stm32mp25: add security clocks
  clk: stm32mp2: use of STM32 access controller

* clk-cleanup:
  clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
  clk: lpc32xx: Constify struct regmap_config
  clk: xilinx: Constify struct regmap_config
  dt-bindings: clock: sprd,sc9860-clk: convert to YAML
  dt-bindings: clock: qoriq-clock: convert to yaml format
  clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro
  clk: sifive: prci: fix module autoloading
  dt-bindings: clock: milbeaut: Drop providers and consumers from example
  clk: sprd: add missing MODULE_DESCRIPTION() macro
  clk: sophgo: add missing MODULE_DESCRIPTION() macro

* clk-kunit:
  clk: disable clk gate tests for s390
  clk: test: add missing MODULE_DESCRIPTION() macros

* clk-mediatek:
  clk: en7523: fix rate divider for slic and spi clocks
  clk: en7523: Remove PCIe reset open drain configuration for EN7581
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
  clk: en7523: Add reset-controller support for EN7581 SoC
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
  clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
  dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
  clk: mediatek: Add a module description where missing
parents a542e9d7 12b02b63 a6c3da03 58c53d43

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml

+24 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ properties: 


  reg:

    minItems: 2

    maxItems: 3

    maxItems: 4



  "#clock-cells":

    description:
@@ -43,6 +43,10 @@ properties: 
      clocks.

    const: 1



  '#reset-cells':

    description: ID of the controller reset line

    const: 1



required:

  - compatible

  - reg
@@ -60,6 +64,8 @@ allOf: 
            - description: scu base address

            - description: misc scu base address



        '#reset-cells': false



  - if:

      properties:

        compatible:
@@ -70,6 +76,7 @@ allOf: 
          items:

            - description: scu base address

            - description: misc scu base address

            - description: reset base address

            - description: pb scu base address



additionalProperties: false
@@ -83,3 +90,19 @@ examples: 
            <0x1fb00000 0x1000>;

      #clock-cells = <1>;

    };



  - |

    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      scuclk: clock-controller@1fa20000 {

        compatible = "airoha,en7581-scu";

        reg = <0x0 0x1fa20000 0x0 0x400>,

              <0x0 0x1fb00000 0x0 0x90>,

              <0x0 0x1fb00830 0x0 0x8>,

              <0x0 0x1fbe3400 0x0 0xfc>;

              #clock-cells = <1>;

              #reset-cells = <1>;

      };

    };

Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml

0 → 100644
+84 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Legacy Clock Block on Freescale QorIQ Platforms



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description: |

  These nodes are deprecated.  Kernels should continue to support

  device trees with these nodes, but new device trees should not use them.



  Most of the bindings are from the common clock binding[1].

  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt



properties:

  compatible:

    enum:

      - fsl,qoriq-core-pll-1.0

      - fsl,qoriq-core-pll-2.0

      - fsl,qoriq-core-mux-1.0

      - fsl,qoriq-core-mux-2.0

      - fsl,qoriq-sysclk-1.0

      - fsl,qoriq-sysclk-2.0

      - fsl,qoriq-platform-pll-1.0

      - fsl,qoriq-platform-pll-2.0



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 4



  clock-names:

    minItems: 1

    maxItems: 4



  clock-output-names:

    minItems: 1

    maxItems: 8



  '#clock-cells':

    minimum: 0

    maximum: 1



required:

  - compatible

  - '#clock-cells'



additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,qoriq-sysclk-1.0

              - fsl,qoriq-sysclk-2.0

    then:

      properties:

        '#clock-cells':

          const: 0



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,qoriq-core-pll-1.0

              - fsl,qoriq-core-pll-2.0

    then:

      properties:

        '#clock-cells':

          const: 1

          description: |

            * 0 - equal to the PLL frequency

            * 1 - equal to the PLL frequency divided by 2

            * 2 - equal to the PLL frequency divided by 4

Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml

0 → 100644
+207 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Clock Block on Freescale QorIQ Platforms



maintainers:

  - Frank Li <Frank.Li@nxp.com>



description: |

  Freescale QorIQ chips take primary clocking input from the external

  SYSCLK signal. The SYSCLK input (frequency) is multiplied using

  multiple phase locked loops (PLL) to create a variety of frequencies

  which can then be passed to a variety of internal logic, including

  cores and peripheral IP blocks.

  Please refer to the Reference Manual for details.



  All references to "1.0" and "2.0" refer to the QorIQ chassis version to

  which the chip complies.



  Chassis Version    Example Chips

  ---------------    -------------

       1.0          p4080, p5020, p5040

       2.0          t4240



  Clock Provider



  The clockgen node should act as a clock provider, though in older device

  trees the children of the clockgen node are the clock providers.



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - fsl,p2041-clockgen

              - fsl,p3041-clockgen

              - fsl,p4080-clockgen

              - fsl,p5020-clockgen

              - fsl,p5040-clockgen

          - const: fsl,qoriq-clockgen-1.0

      - items:

          - enum:

              - fsl,t1023-clockgen

              - fsl,t1024-clockgen

              - fsl,t1040-clockgen

              - fsl,t1042-clockgen

              - fsl,t2080-clockgen

              - fsl,t2081-clockgen

              - fsl,t4240-clockgen

          - const: fsl,qoriq-clockgen-2.0

      - items:

          - enum:

              - fsl,b4420-clockgen

              - fsl,b4860-clockgen

          - const: fsl,b4-clockgen

      - items:

          - enum:

              - fsl,ls1012a-clockgen

              - fsl,ls1021a-clockgen

              - fsl,ls1028a-clockgen

              - fsl,ls1043a-clockgen

              - fsl,ls1046a-clockgen

              - fsl,ls1088a-clockgen

              - fsl,ls2080a-clockgen

              - fsl,lx2160a-clockgen



  reg:

    maxItems: 1



  ranges: true



  '#address-cells':

    const: 1



  '#size-cells':

    const: 1



  '#clock-cells':

    const: 2

    description: |

      The first cell of the clock specifier is the clock type, and the

      second cell is the clock index for the specified type.



        Type#  Name       Index Cell

        0  sysclk          must be 0

        1  cmux            index (n in CLKCnCSR)

        2  hwaccel         index (n in CLKCGnHWACSR)

        3  fman            0 for fm1, 1 for fm2

        4  platform pll    n=pll/(n+1). For example, when n=1,

                          that means output_freq=PLL_freq/2.

        5  coreclk         must be 0



  clock-frequency:

    description: Input system clock frequency (SYSCLK)



  clocks:

    items:

      - description:

          sysclk may be provided as an input clock.  Either clock-frequency

          or clocks must be provided.

      - description:

          A second input clock, called "coreclk", may be provided if

          core PLLs are based on a different input clock from the

          platform PLL.

    minItems: 1



  clock-names:

    items:

      - const: sysclk

      - const: coreclk



patternProperties:

  '^mux[0-9]@[a-f0-9]+$':

    deprecated: true

    $ref: fsl,qoriq-clock-legacy.yaml



  '^sysclk(-[a-z0-9]+)?$':

    deprecated: true

    $ref: fsl,qoriq-clock-legacy.yaml



  '^pll[0-9]@[a-f0-9]+$':

    deprecated: true

    $ref: fsl,qoriq-clock-legacy.yaml



  '^platform\-pll@[a-f0-9]+$':

    deprecated: true

    $ref: fsl,qoriq-clock-legacy.yaml



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    /* clock provider example */

    global-utilities@e1000 {

        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";

        reg = <0xe1000 0x1000>;

        clock-frequency = <133333333>;

        #clock-cells = <2>;

    };



  - |

    /* Legacy example */

    global-utilities@e1000 {

        compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";

        reg = <0xe1000 0x1000>;

        ranges = <0x0 0xe1000 0x1000>;

        clock-frequency = <133333333>;

        #address-cells = <1>;

        #size-cells = <1>;

        #clock-cells = <2>;



        sysclk: sysclk {

            compatible = "fsl,qoriq-sysclk-1.0";

            clock-output-names = "sysclk";

            #clock-cells = <0>;

        };



        pll0: pll0@800 {

            compatible = "fsl,qoriq-core-pll-1.0";

            reg = <0x800 0x4>;

            #clock-cells = <1>;

            clocks = <&sysclk>;

            clock-output-names = "pll0", "pll0-div2";

        };



        pll1: pll1@820 {

            compatible = "fsl,qoriq-core-pll-1.0";

            reg = <0x820 0x4>;

            #clock-cells = <1>;

            clocks = <&sysclk>;

            clock-output-names = "pll1", "pll1-div2";

        };



        mux0: mux0@0 {

            compatible = "fsl,qoriq-core-mux-1.0";

            reg = <0x0 0x4>;

            #clock-cells = <0>;

            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

            clock-output-names = "cmux0";

        };



        mux1: mux1@20 {

            compatible = "fsl,qoriq-core-mux-1.0";

            reg = <0x20 0x4>;

            #clock-cells = <0>;

            clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

            clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

            clock-output-names = "cmux1";

        };



        platform-pll@c00 {

            #clock-cells = <1>;

            reg = <0xc00 0x4>;

            compatible = "fsl,qoriq-platform-pll-1.0";

            clocks = <&sysclk>;

            clock-output-names = "platform-pll", "platform-pll-div2";

        };

    };

Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml

+6 −4
Original line number Diff line number Diff line
@@ -14,9 +14,11 @@ maintainers: 


properties:

  compatible:

    enum:

      - mediatek,mt7622-pciesys

      - mediatek,mt7629-pciesys

    oneOf:

      - items:

          - const: mediatek,mt7622-pciesys

          - const: syscon

      - const: mediatek,mt7629-pciesys



  reg:

    maxItems: 1
@@ -38,7 +40,7 @@ additionalProperties: false 
examples:

  - |

    clock-controller@1a100800 {

        compatible = "mediatek,mt7622-pciesys";

        compatible = "mediatek,mt7622-pciesys", "syscon";

        reg = <0x1a100800 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml

+3 −0
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ properties: 
  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg