Unverified Commit 1672b065 authored by James Clark's avatar James Clark Committed by Mark Brown
Browse files

spi: spi-fsl-dspi: Define regmaps per device 



Refactor the regmaps so they can be defined per device rather than
programmatically. This will allow us to add two new regmaps for S32G in
a later commit.

No functional changes.

Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Signed-off-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-5-bea884630cfb@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 87a14a96

drivers/spi/spi-fsl-dspi.c

+74 −62
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ struct fsl_dspi_devtype_data { 
	enum dspi_trans_mode	trans_mode;

	u8			max_clock_factor;

	int			fifo_size;

	const struct regmap_config *regmap;

};



enum {
@@ -137,60 +138,130 @@ enum { 
	VF610,

};



static const struct regmap_range dspi_yes_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_MCR),

	regmap_reg_range(SPI_TCR, SPI_CTAR(3)),

	regmap_reg_range(SPI_SR, SPI_TXFR3),

	regmap_reg_range(SPI_RXFR0, SPI_RXFR3),

	regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_access_table = {

	.yes_ranges	= dspi_yes_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_yes_ranges),

};



static const struct regmap_range dspi_volatile_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_TCR),

	regmap_reg_range(SPI_SR, SPI_SR),

	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_volatile_table = {

	.yes_ranges	= dspi_volatile_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),

};



enum {

	DSPI_REGMAP,

	DSPI_XSPI_REGMAP,

	DSPI_PUSHR,

};



static const struct regmap_config dspi_regmap_config[] = {

	[DSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_RXFR3,

		.volatile_table	= &dspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	[DSPI_XSPI_REGMAP] = {

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_SREX,

		.volatile_table	= &dspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	[DSPI_PUSHR] = {

		.name		= "pushr",

		.reg_bits	= 16,

		.val_bits	= 16,

		.reg_stride	= 2,

		.max_register	= 0x2,

	},

};



static const struct fsl_dspi_devtype_data devtype_data[] = {

	[VF610] = {

		.trans_mode		= DSPI_DMA_MODE,

		.max_clock_factor	= 2,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_REGMAP],

	},

	[LS1021A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1012A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1028A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1043A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS1046A] = {

		/* Has A-011218 DMA erratum */

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS2080A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LS2085A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[LX2160A] = {

		.trans_mode		= DSPI_XSPI_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 4,

		.regmap			= &dspi_regmap_config[DSPI_XSPI_REGMAP],

	},

	[MCF5441X] = {

		.trans_mode		= DSPI_DMA_MODE,

		.max_clock_factor	= 8,

		.fifo_size		= 16,

		.regmap			= &dspi_regmap_config[DSPI_REGMAP],

	},

};
@@ -1191,61 +1262,6 @@ static int dspi_resume(struct device *dev) 


static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);



static const struct regmap_range dspi_yes_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_MCR),

	regmap_reg_range(SPI_TCR, SPI_CTAR(3)),

	regmap_reg_range(SPI_SR, SPI_TXFR3),

	regmap_reg_range(SPI_RXFR0, SPI_RXFR3),

	regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_access_table = {

	.yes_ranges	= dspi_yes_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_yes_ranges),

};



static const struct regmap_range dspi_volatile_ranges[] = {

	regmap_reg_range(SPI_MCR, SPI_TCR),

	regmap_reg_range(SPI_SR, SPI_SR),

	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),

	regmap_reg_range(SPI_SREX, SPI_SREX),

};



static const struct regmap_access_table dspi_volatile_table = {

	.yes_ranges	= dspi_volatile_ranges,

	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),

};



static const struct regmap_config dspi_regmap_config = {

	.reg_bits	= 32,

	.val_bits	= 32,

	.reg_stride	= 4,

	.max_register	= SPI_RXFR3,

	.volatile_table	= &dspi_volatile_table,

	.rd_table	= &dspi_access_table,

	.wr_table	= &dspi_access_table,

};



static const struct regmap_config dspi_xspi_regmap_config[] = {

	{

		.reg_bits	= 32,

		.val_bits	= 32,

		.reg_stride	= 4,

		.max_register	= SPI_SREX,

		.volatile_table	= &dspi_volatile_table,

		.rd_table	= &dspi_access_table,

		.wr_table	= &dspi_access_table,

	},

	{

		.name		= "pushr",

		.reg_bits	= 16,

		.val_bits	= 16,

		.reg_stride	= 2,

		.max_register	= 0x2,

	},

};



static int dspi_init(struct fsl_dspi *dspi)

{

	unsigned int mcr;
@@ -1305,7 +1321,6 @@ static int dspi_target_abort(struct spi_controller *host) 
static int dspi_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;

	const struct regmap_config *regmap_config;

	struct fsl_dspi_platform_data *pdata;

	struct spi_controller *ctlr;

	int ret, cs_num, bus_num = -1;
@@ -1388,11 +1403,8 @@ static int dspi_probe(struct platform_device *pdev) 
		goto out_ctlr_put;

	}



	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)

		regmap_config = &dspi_xspi_regmap_config[0];

	else

		regmap_config = &dspi_regmap_config;

	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);

	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base,

					     dspi->devtype_data->regmap);

	if (IS_ERR(dspi->regmap)) {

		dev_err(&pdev->dev, "failed to init regmap: %ld\n",

				PTR_ERR(dspi->regmap));
@@ -1403,7 +1415,7 @@ static int dspi_probe(struct platform_device *pdev) 
	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {

		dspi->regmap_pushr = devm_regmap_init_mmio(

			&pdev->dev, base + SPI_PUSHR,

			&dspi_xspi_regmap_config[1]);

			&dspi_regmap_config[DSPI_PUSHR]);

		if (IS_ERR(dspi->regmap_pushr)) {

			dev_err(&pdev->dev,

				"failed to init pushr regmap: %ld\n",