Commit 1679bfef authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom-qmp-ufs: Add SM8550 support 



Add SM8550 specific register layout and table configs.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-7-abel.vesa@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5b8154ce

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+96 −0
Original line number Diff line number Diff line
@@ -103,6 +103,13 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,

};



static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_START_CTRL]		= QPHY_V6_PCS_UFS_PHY_START,

	[QPHY_PCS_READY_STATUS]		= QPHY_V6_PCS_UFS_READY_STATUS,

	[QPHY_SW_RESET]			= QPHY_V6_PCS_UFS_SW_RESET,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,

};



static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
@@ -607,6 +614,61 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),

};



static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),

};



static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),

};



static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),



	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),



	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),



	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),

};



static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



struct qmp_ufs_offsets {

	u16 serdes;

	u16 pcs;
@@ -729,6 +791,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets = { 
	.rx2		= 0xa00,

};



static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {

	.serdes		= 0,

	.pcs		= 0x0400,

	.tx		= 0x1000,

	.rx		= 0x1200,

	.tx2		= 0x1800,

	.rx2		= 0x1a00,

};



static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {

	.lanes			= 1,
@@ -968,6 +1039,28 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 
	.regs			= ufsphy_v5_regs_layout,

};



static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_ufs_offsets_v6,



	.tbls = {

		.serdes		= sm8550_ufsphy_serdes,

		.serdes_num	= ARRAY_SIZE(sm8550_ufsphy_serdes),

		.tx		= sm8550_ufsphy_tx,

		.tx_num		= ARRAY_SIZE(sm8550_ufsphy_tx),

		.rx		= sm8550_ufsphy_rx,

		.rx_num		= ARRAY_SIZE(sm8550_ufsphy_rx),

		.pcs		= sm8550_ufsphy_pcs,

		.pcs_num	= ARRAY_SIZE(sm8550_ufsphy_pcs),

	},

	.clk_list		= sdm845_ufs_phy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= ufsphy_v6_regs_layout,

};



static void qmp_ufs_configure_lane(void __iomem *base,

					const struct qmp_phy_init_tbl tbl[],

					int num,
@@ -1479,6 +1572,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8450-qmp-ufs-phy",

		.data = &sm8450_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm8550-qmp-ufs-phy",

		.data = &sm8550_ufsphy_cfg,

	},

	{ },

};