Commit 16a93594 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Implement transcoder LRR for TGL+ 



Implement low refresh rate (LRR) where we change the vblank
length by hand as requested, but otherwise keep the timing
generator running in non-VRR mode (ie. fixed refresh rate).

The panel itself must support VRR for this to work, and
only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
we need to make the switch properly. The double buffer
latching happens at the start of transcoders undelayed
vblank. The other thing that we change is
TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
that in DP mode. But I decided to keep writing it anyway
just to avoid more special cases in readout/state check.

v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
    the hardware
v3: Reconcile with VRR fastset
    Adjust update_lrr flag behaviour
    Make sure timings stay within VRR range
v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
    Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)

TODO: Hook LRR into the automatic DRRS downclocking stuff?

Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230915103800.14218-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarManasi Navare <navaremanasi@chromium.org>
parent 26f03ef8

drivers/gpu/drm/i915/display/intel_atomic.c

+1 −0
Original line number Diff line number Diff line
@@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) 


	crtc_state->update_pipe = false;

	crtc_state->update_m_n = false;

	crtc_state->update_lrr = false;

	crtc_state->disable_lp_wm = false;

	crtc_state->disable_cxsr = false;

	crtc_state->update_wm_pre = false;

drivers/gpu/drm/i915/display/intel_crtc.c

+5 −4
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state, 
	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {

		/* timing changes should happen with VRR disabled */

		drm_WARN_ON(state->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||

			    new_crtc_state->update_m_n);

			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);



		if (intel_vrr_is_push_sent(crtc_state))

			*vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
@@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state, 
	*max = *vblank_start - 1;



	/*

	 * M/N is double buffered on the transcoder's undelayed vblank,

	 * so with seamless M/N we must evade both vblanks.

	 * M/N and TRANS_VTOTAL are double buffered on the transcoder's

	 * undelayed vblank, so with seamless M/N and LRR we must evade

	 * both vblanks.

	 */

	if (new_crtc_state->update_m_n)

	if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)

		*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;

}

drivers/gpu/drm/i915/display/intel_display.c

+55 −5
Original line number Diff line number Diff line
@@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 
{

	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||

		(new_crtc_state->vrr.enable &&

		 (new_crtc_state->update_m_n ||

		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||

		  vrr_params_changed(old_crtc_state, new_crtc_state)));

}
@@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 
{

	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||

		(old_crtc_state->vrr.enable &&

		 (new_crtc_state->update_m_n ||

		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||

		  vrr_params_changed(old_crtc_state, new_crtc_state)));

}
@@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta 
			       VTOTAL(crtc_vtotal - 1));

}



static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;



	crtc_vdisplay = adjusted_mode->crtc_vdisplay;

	crtc_vtotal = adjusted_mode->crtc_vtotal;

	crtc_vblank_start = adjusted_mode->crtc_vblank_start;

	crtc_vblank_end = adjusted_mode->crtc_vblank_end;



	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);



	/*

	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.

	 * But let's write it anyway to keep the state checker happy.

	 */

	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),

		       VBLANK_START(crtc_vblank_start - 1) |

		       VBLANK_END(crtc_vblank_end - 1));

	/*

	 * The double buffer latch point for TRANS_VTOTAL

	 * is the transcoder's undelayed vblank.

	 */

	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),

		       VACTIVE(crtc_vdisplay - 1) |

		       VTOTAL(crtc_vtotal - 1));

}



static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -5082,11 +5113,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \

	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \

	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \

	PIPE_CONF_CHECK_I(name.crtc_vtotal); \

	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \

	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \

	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \

	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \

	if (!fastset || !pipe_config->update_lrr) { \

		PIPE_CONF_CHECK_I(name.crtc_vtotal); \

		PIPE_CONF_CHECK_I(name.crtc_vblank_end); \

	} \

} while (0)



#define PIPE_CONF_CHECK_RECT(name) do { \
@@ -5452,6 +5485,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state, 
		crtc_state->uapi.mode_changed = true;

		crtc_state->update_pipe = false;

		crtc_state->update_m_n = false;

		crtc_state->update_lrr = false;



		ret = drm_atomic_add_affected_connectors(&state->base,

							 &crtc->base);
@@ -5569,6 +5603,10 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta 
{

	struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);



	/* only allow LRR when the timings stay within the VRR range */

	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)

		new_crtc_state->update_lrr = false;



	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))

		drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");

	else
@@ -5579,6 +5617,11 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta 
				   &new_crtc_state->dp_m_n))

		new_crtc_state->update_m_n = false;



	if (intel_crtc_needs_modeset(new_crtc_state) ||

	    (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&

	     old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))

		new_crtc_state->update_lrr = false;



	if (!intel_crtc_needs_modeset(new_crtc_state))

		new_crtc_state->update_pipe = true;

}
@@ -6294,6 +6337,7 @@ int intel_atomic_check(struct drm_device *dev, 
				new_crtc_state->uapi.mode_changed = true;

				new_crtc_state->update_pipe = false;

				new_crtc_state->update_m_n = false;

				new_crtc_state->update_lrr = false;

			}

		}
@@ -6307,6 +6351,7 @@ int intel_atomic_check(struct drm_device *dev, 
				new_crtc_state->uapi.mode_changed = true;

				new_crtc_state->update_pipe = false;

				new_crtc_state->update_m_n = false;

				new_crtc_state->update_lrr = false;

			}

		}
@@ -6315,6 +6360,7 @@ int intel_atomic_check(struct drm_device *dev, 
				new_crtc_state->uapi.mode_changed = true;

				new_crtc_state->update_pipe = false;

				new_crtc_state->update_m_n = false;

				new_crtc_state->update_lrr = false;

			}

		}

	}
@@ -6496,6 +6542,9 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 
	if (new_crtc_state->update_m_n)

		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,

					       &new_crtc_state->dp_m_n);



	if (new_crtc_state->update_lrr)

		intel_set_transcoder_timings_lrr(new_crtc_state);

}



static void commit_pipe_pre_planes(struct intel_atomic_state *state,
@@ -6632,7 +6681,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, 
	 *

	 * FIXME Should be synchronized with the start of vblank somehow...

	 */

	if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)

	if (vrr_enabling(old_crtc_state, new_crtc_state) ||

	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)

		intel_crtc_update_active_timings(new_crtc_state,

						 new_crtc_state->vrr.enable);

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ struct drm_printer; 
#define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))

#define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)

#define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))

#define HAS_LRR(i915)			(DISPLAY_VER(i915) >= 12)

#define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))

#define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)

#define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −1
Original line number Diff line number Diff line
@@ -1084,6 +1084,7 @@ struct intel_crtc_state { 
	unsigned fb_bits; /* framebuffers to flip */

	bool update_pipe; /* can a fast modeset be performed? */

	bool update_m_n; /* update M/N seamlessly during fastset? */

	bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */

	bool disable_cxsr;

	bool update_wm_pre, update_wm_post; /* watermarks are updated */

	bool fifo_changed; /* FIFO split is changed */
@@ -1385,7 +1386,7 @@ struct intel_crtc_state { 


	/* Variable Refresh Rate state */

	struct {

		bool enable;

		bool enable, in_range;

		u8 pipeline_full;

		u16 flipline, vmin, vmax, guardband;

	} vrr;