Unverified Commit 16be14ee authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Rodrigo Vivi
Browse files

drm/xe: Define CACHE_MODE_1 as MCR register 



CACHE_MODE_1 is a MCR register for all platforms that currently use it
in the Xe driver.  Use XE_REG_MCR() when defining it.

Fixes: 8cd7e975 ("drm/xe: Add missing DG2 lrc workarounds")
Fixes: ff063430 ("drm/xe/mtl: Add some initial MTL workarounds")
Bspec: 66534, 67788
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-1-30dd47855fee@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit 8f765f0c054e0fb39980a76b4c899b027395929d)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 96bf49b5

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ 


#define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)



#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)

#define CACHE_MODE_1				XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED)

#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)



#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)