Commit 17019d51 authored by Manali Shukla's avatar Manali Shukla Committed by Sean Christopherson
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KVM: selftests: Treat AMD Family 17h+ as supporting branch insns retired 



When detecting AMD PMU support for encoding "branch instructions retired"
as event 0xc2,0, simply check for Family 17h+ as all Zen CPUs support said
encoding, and AMD will maintain the encoding for backwards compatibility
on future CPUs.

Note, the kernel proper also interprets Family 17h+ as Zen (see the sole
caller of init_amd_zen_common()).

Suggested-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarManali Shukla <manali.shukla@amd.com>
Link: https://lore.kernel.org/r/20240605050835.30491-1-manali.shukla@amd.com


Co-developed-by: default avatarSean Christopherson <seanjc@google.com>
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent f626279d

tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c

+5 −30
Original line number Diff line number Diff line
@@ -32,8 +32,8 @@ struct __kvm_pmu_event_filter { 


/*

 * This event list comprises Intel's known architectural events, plus AMD's

 * "retired branch instructions" for Zen1-Zen3 (and* possibly other AMD CPUs).

 * Note, AMD and Intel use the same encoding for instructions retired.

 * Branch Instructions Retired for Zen CPUs.  Note, AMD and Intel use the

 * same encoding for Instructions Retired.

 */

kvm_static_assert(INTEL_ARCH_INSTRUCTIONS_RETIRED == AMD_ZEN_INSTRUCTIONS_RETIRED);
@@ -353,38 +353,13 @@ static bool use_intel_pmu(void) 
	       kvm_pmu_has(X86_PMU_FEATURE_BRANCH_INSNS_RETIRED);

}



static bool is_zen1(uint32_t family, uint32_t model)

{

	return family == 0x17 && model <= 0x0f;

}



static bool is_zen2(uint32_t family, uint32_t model)

{

	return family == 0x17 && model >= 0x30 && model <= 0x3f;

}



static bool is_zen3(uint32_t family, uint32_t model)

{

	return family == 0x19 && model <= 0x0f;

}



/*

 * Determining AMD support for a PMU event requires consulting the AMD

 * PPR for the CPU or reference material derived therefrom. The AMD

 * test code herein has been verified to work on Zen1, Zen2, and Zen3.

 *

 * Feel free to add more AMD CPUs that are documented to support event

 * select 0xc2 umask 0 as "retired branch instructions."

 * On AMD, all Family 17h+ CPUs (Zen and its successors) use event encoding

 * 0xc2,0 for Branch Instructions Retired.

 */

static bool use_amd_pmu(void)

{

	uint32_t family = kvm_cpu_family();

	uint32_t model = kvm_cpu_model();



	return host_cpu_is_amd &&

		(is_zen1(family, model) ||

		 is_zen2(family, model) ||

		 is_zen3(family, model));

	return host_cpu_is_amd && kvm_cpu_family() >= 0x17;

}



/*