Commit 1717cc5f authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher
Browse files

drm/amd: Fix initialization mistake for NBIO 7.3.0 



The same strapping initialization issue that happened on NBIO 7.5.1
appears to be happening on NBIO 7.3.0.
Apply the same fix to 7.3.0 as well.

Note: This workaround relies upon the integrated GPU being enabled
in BIOS. If the integrated GPU is disabled in BIOS a different
workaround will be required.

Reported-by: default avatarThomas Glanzmann <thomas@glanzmann.de>
Cc: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#u


Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 93bb18d2

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

+9 −5
Original line number Diff line number Diff line
@@ -382,11 +382,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 
		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);

		break;

	case IP_VERSION(7, 5, 1):

		data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);

		data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;

		WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);

		fallthrough;

	default:

		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));

		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
@@ -399,6 +394,15 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 
		break;

	}



	switch (adev->ip_versions[NBIO_HWIP][0]) {

	case IP_VERSION(7, 3, 0):

	case IP_VERSION(7, 5, 1):

		data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);

		data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;

		WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);

		break;

	}



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

			regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;