Commit 1725f0eb authored by David Wu's avatar David Wu Committed by Jakub Kicinski
Browse files

net: stmmac: dwmac-rk: Add GMAC support for RK3528 



Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.

Add initial support for the RK3528 GMAC variant.

Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Signed-off-by: default avatarJonas Karlman <jonas@kwiboo.se>
Link: https://patch.msgid.link/20250319214415.3086027-3-jonas@kwiboo.se


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 1b22f686

drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

+132 −0
Original line number Diff line number Diff line
@@ -828,6 +828,137 @@ static const struct rk_gmac_ops rk3399_ops = { 
	.set_rmii_speed = rk3399_set_rmii_speed,

};



#define RK3528_VO_GRF_GMAC_CON		0x0018

#define RK3528_VO_GRF_MACPHY_CON0	0x001c

#define RK3528_VO_GRF_MACPHY_CON1	0x0020

#define RK3528_VPU_GRF_GMAC_CON5	0x0018

#define RK3528_VPU_GRF_GMAC_CON6	0x001c



#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)

#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)

#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)

#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)



#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)

#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)



#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)

#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)

#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)



#define RK3528_GMAC1_CLK_SELECT_CRU	GRF_CLR_BIT(12)

#define RK3528_GMAC1_CLK_SELECT_IO	GRF_BIT(12)



#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)

#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)

#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)

#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)



#define RK3528_GMAC1_CLK_RGMII_DIV1	(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))

#define RK3528_GMAC1_CLK_RGMII_DIV5	(GRF_BIT(11) | GRF_BIT(10))

#define RK3528_GMAC1_CLK_RGMII_DIV50	(GRF_BIT(11) | GRF_CLR_BIT(10))



#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)

#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)

#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)

#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)



static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,

				int tx_delay, int rx_delay)

{

	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);



	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));



	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,

		     RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |

		     RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));

}



static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)

{

	if (bsp_priv->id == 1)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_PHY_INTF_SEL_RMII);

	else

		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,

			     RK3528_GMAC0_PHY_INTF_SEL_RMII |

			     RK3528_GMAC0_CLK_RMII_DIV2);

}



static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;



	if (speed == 10)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV50);

	else if (speed == 100)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV5);

	else if (speed == 1000)

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,

			     RK3528_GMAC1_CLK_RGMII_DIV1);

	else

		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);

}



static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)

{

	struct device *dev = &bsp_priv->pdev->dev;

	unsigned int reg, val;



	if (speed == 10)

		val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :

					  RK3528_GMAC0_CLK_RMII_DIV20;

	else if (speed == 100)

		val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :

					  RK3528_GMAC0_CLK_RMII_DIV2;

	else {

		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);

		return;

	}



	reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :

				  RK3528_VO_GRF_GMAC_CON;



	regmap_write(bsp_priv->grf, reg, val);

}



static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,

				       bool input, bool enable)

{

	unsigned int val;



	if (bsp_priv->id == 1) {

		val = input ? RK3528_GMAC1_CLK_SELECT_IO :

			      RK3528_GMAC1_CLK_SELECT_CRU;

		val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :

				RK3528_GMAC1_CLK_RMII_GATE;

		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);

	} else {

		val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :

			       RK3528_GMAC0_CLK_RMII_GATE;

		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);

	}

}



static const struct rk_gmac_ops rk3528_ops = {

	.set_to_rgmii = rk3528_set_to_rgmii,

	.set_to_rmii = rk3528_set_to_rmii,

	.set_rgmii_speed = rk3528_set_rgmii_speed,

	.set_rmii_speed = rk3528_set_rmii_speed,

	.set_clock_selection = rk3528_set_clock_selection,

	.regs_valid = true,

	.regs = {

		0xffbd0000, /* gmac0 */

		0xffbe0000, /* gmac1 */

		0x0, /* sentinel */

	},

};



#define RK3568_GRF_GMAC0_CON0		0x0380

#define RK3568_GRF_GMAC0_CON1		0x0384

#define RK3568_GRF_GMAC1_CON0		0x0388
@@ -1819,6 +1950,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = { 
	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },

	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },

	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },

	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },

	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },

	{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },

	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },