Commit 1741281a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx10: add ring reset callbacks 



Add ring reset callbacks for gfx and compute.

v2: fix gfx handling
v3: wait for KIQ to complete

Acked-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a10c9393

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+91 −0
Original line number Diff line number Diff line
@@ -9416,6 +9416,95 @@ static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 
		amdgpu_ring_write(ring, ring->funcs->nop);

}



static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];

	struct amdgpu_ring *kiq_ring = &kiq->ring;

	unsigned long flags;

	u32 tmp;

	u64 addr;

	int r;



	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)

		return -EINVAL;



	spin_lock_irqsave(&kiq->ring_lock, flags);



	if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {

		spin_unlock_irqrestore(&kiq->ring_lock, flags);

		return -ENOMEM;

	}



	addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +

		offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);

	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

	if (ring->pipe == 0)

		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);

	else

		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);



	gfx_v10_0_ring_emit_wreg(kiq_ring,

				 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);

	gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,

			       lower_32_bits(addr), upper_32_bits(addr),

			       0, 1, 0x20);

	gfx_v10_0_ring_emit_reg_wait(kiq_ring,

				     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);

	kiq->pmf->kiq_map_queues(kiq_ring, ring);

	amdgpu_ring_commit(kiq_ring);



	spin_unlock_irqrestore(&kiq->ring_lock, flags);



	r = amdgpu_ring_test_ring(kiq_ring);

	if (r)

		return r;



	/* reset the ring */

	ring->wptr = 0;

	*ring->wptr_cpu_addr = 0;

	amdgpu_ring_clear_ring(ring);



	return amdgpu_ring_test_ring(ring);

}



static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,

			       unsigned int vmid)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];

	struct amdgpu_ring *kiq_ring = &kiq->ring;

	unsigned long flags;

	int r;



	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)

		return -EINVAL;



	spin_lock_irqsave(&kiq->ring_lock, flags);



	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {

		spin_unlock_irqrestore(&kiq->ring_lock, flags);

		return -ENOMEM;

	}



	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,

				   0, 0);

	amdgpu_ring_commit(kiq_ring);



	spin_unlock_irqrestore(&kiq->ring_lock, flags);



	r = amdgpu_ring_test_ring(kiq_ring);

	if (r)

		return r;



	/* reset the ring */

	ring->wptr = 0;

	*ring->wptr_cpu_addr = 0;

	amdgpu_ring_clear_ring(ring);



	return amdgpu_ring_test_ring(ring);

}



static void gfx_v10_ip_print(void *handle, struct drm_printer *p)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9619,6 +9708,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 
	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,

	.soft_recovery = gfx_v10_0_ring_soft_recovery,

	.emit_mem_sync = gfx_v10_0_emit_mem_sync,

	.reset = gfx_v10_0_reset_kgq,

};



static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
@@ -9655,6 +9745,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 
	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,

	.soft_recovery = gfx_v10_0_ring_soft_recovery,

	.emit_mem_sync = gfx_v10_0_emit_mem_sync,

	.reset = gfx_v10_0_reset_kcq,

};



static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {