Commit 177deeea authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/ltphy: Nuke bogus weird timeouts 



The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
ways. Get rid of the weird fast timeouts, and just use the slow ones.
For consistency with intel_wait_for_register() we'll stick to the
default 2 usec fast timeout for all cases.

Someone really needs to properly document where all these magic numbers
came from...

This will let us eventually nuke intel_de_wait_custom() and convert
over to poll_timeout_us().

v2: Go for the longer (ms) timeout in case it actually matters

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-9-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d4270f09

drivers/gpu/drm/i915/display/intel_lt_phy.c

+5 −6
Original line number Diff line number Diff line
@@ -1178,8 +1178,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, 
	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),

				 XELPDP_LANE_PCLK_PLL_ACK(0),

				 XELPDP_LANE_PCLK_PLL_ACK(0),

				 XE3PLPD_MACCLK_TURNON_LATENCY_US,

				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))

				 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))

		drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",

			 phy_name(phy));
@@ -1192,13 +1191,13 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, 


	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),

				 lane_phy_current_status, 0,

				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))

				 2, XE3PLPD_RESET_END_LATENCY_MS, NULL))

		drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",

			 phy_name(phy));



	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),

				 lane_phy_pulse_status, lane_phy_pulse_status,

				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))

				 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))

		drm_warn(display->drm, "PHY %c PLL rate not changed\n",

			 phy_name(phy));
@@ -1673,7 +1672,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 
		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),

					 XELPDP_LANE_PCLK_PLL_ACK(0),

					 XELPDP_LANE_PCLK_PLL_ACK(0),

					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))

					 2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))

			drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",

				 phy_name(phy));
@@ -1701,7 +1700,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 
		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */

		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),

					 lane_phy_pulse_status, lane_phy_pulse_status,

					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))

					 2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))

			drm_warn(display->drm, "PHY %c PLL rate not changed\n",

				 phy_name(phy));

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

+3 −4
Original line number Diff line number Diff line
@@ -7,13 +7,12 @@ 
#define __INTEL_LT_PHY_REGS_H__



#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500

#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1

#define XE3PLPD_MACCLK_TURNON_LATENCY_US	21

#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	2

#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1

#define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

#define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS	1

#define XE3PLPD_RESET_START_LATENCY_US	10

#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US	4

#define XE3PLPD_RESET_END_LATENCY_US		200

#define XE3PLPD_RESET_END_LATENCY_MS		2



/* LT Phy MAC Register */

#define LT_PHY_MAC_VDR			_MMIO(0xC00)