Commit 17aa34e8 authored by Junhao He's avatar Junhao He Committed by Will Deacon
Browse files

drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver 



HiSilicon DDRC v3 PMU has the different interrupt register offset
compared to the v2. Add device information of v3 PMU with ACPI
HID HISI0235.

Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20250619125557.57372-3-yangyicong@huawei.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent dc86791f

drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c

+24 −0
Original line number Diff line number Diff line
@@ -43,6 +43,11 @@ 
#define DDRC_V2_EVENT_TYPE	0xe74

#define DDRC_V2_PERF_CTRL	0xeA0



/* DDRC interrupt registers definition in v3 */

#define DDRC_V3_INT_MASK	0x534

#define DDRC_V3_INT_STATUS	0x538

#define DDRC_V3_INT_CLEAR	0x53C



/* DDRC has 8-counters */

#define DDRC_NR_COUNTERS	0x8

#define DDRC_V1_PERF_CTRL_EN	0x2
@@ -460,9 +465,28 @@ static const struct hisi_pmu_dev_info hisi_ddrc_v2 = { 
	.private = &hisi_ddrc_v2_pmu_regs,

};



static struct hisi_ddrc_pmu_regs hisi_ddrc_v3_pmu_regs = {

	.event_cnt = DDRC_V2_EVENT_CNT,

	.event_ctrl = DDRC_V2_EVENT_CTRL,

	.event_type = DDRC_V2_EVENT_TYPE,

	.perf_ctrl = DDRC_V2_PERF_CTRL,

	.perf_ctrl_en = DDRC_V2_PERF_CTRL_EN,

	.int_mask = DDRC_V3_INT_MASK,

	.int_clear = DDRC_V3_INT_CLEAR,

	.int_status = DDRC_V3_INT_STATUS,

};



static const struct hisi_pmu_dev_info hisi_ddrc_v3 = {

	.counter_bits = 48,

	.check_event = DDRC_V2_NR_EVENTS,

	.attr_groups = hisi_ddrc_pmu_v2_attr_groups,

	.private = &hisi_ddrc_v3_pmu_regs,

};



static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] = {

	{ "HISI0233", (kernel_ulong_t)&hisi_ddrc_v1 },

	{ "HISI0234", (kernel_ulong_t)&hisi_ddrc_v2 },

	{ "HISI0235", (kernel_ulong_t)&hisi_ddrc_v3 },

	{}

};

MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match);