Commit 17accf4f authored by Cruise Hung's avatar Cruise Hung Committed by Alex Deucher
Browse files

drm/amd/display: Support external tunneling feature 



[Why & How]
The original code only supports the tunneling for embedded one.
To support external tunneling feature, it needs to check
Tunneling_Support bit register.

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Signed-off-by: default avatarCruise Hung <Cruise.Hung@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fe1903bc

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+4 −0
Original line number Diff line number Diff line
@@ -3911,6 +3911,10 @@ enum dc_status resource_map_pool_resources( 
		if (!dc->link_srv->dp_decide_link_settings(stream,

				&pipe_ctx->link_config.dp_link_settings))

			return DC_FAIL_DP_LINK_BANDWIDTH;



		dc->link_srv->dp_decide_tunnel_settings(stream,

				&pipe_ctx->link_config.dp_tunnel_settings);



		if (dc->link_srv->dp_get_encoding_format(

				&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

			pipe_ctx->stream_res.hpo_dp_stream_enc =

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+21 −0
Original line number Diff line number Diff line
@@ -159,6 +159,11 @@ struct dc_link_settings { 
	uint8_t link_rate_set;

};



struct dc_tunnel_settings {

	bool should_enable_dp_tunneling;

	bool should_use_dp_bw_allocation;

};



union dc_dp_ffe_preset {

	struct {

		uint8_t level		: 4;
@@ -943,10 +948,20 @@ union dpia_info { 
	uint8_t raw;

};



/* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */

union usb4_driver_bw_cap {

	struct {

		uint8_t rsvd :7;

		uint8_t driver_bw_alloc_support :1;

	} bits;

	uint8_t raw;

};



/* DP Tunneling over USB4 */

struct dpcd_usb4_dp_tunneling_info {

	union dp_tun_cap_support dp_tun_cap;

	union dpia_info dpia_info;

	union usb4_driver_bw_cap driver_bw_cap;

	uint8_t usb4_driver_id;

	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];

};
@@ -1486,5 +1501,11 @@ struct dp_trace { 
# ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED

# define DP_TUNNELING_BW_ALLOC_CAP_CHANGED		(1 << 3)

# endif

# ifndef DPTX_BW_ALLOC_UNMASK_IRQ

# define DPTX_BW_ALLOC_UNMASK_IRQ			(1 << 6)

# endif

# ifndef DPTX_BW_ALLOC_MODE_ENABLE

# define DPTX_BW_ALLOC_MODE_ENABLE			(1 << 7)

# endif



#endif /* DC_DP_TYPES_H */

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -1550,7 +1550,7 @@ static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx) 
	struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;

	const struct dc *dc = pipe_ctx->stream->link->dc;



	if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)

	if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)

		return false;



	// Not necessary for MST configurations

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+2 −0
Original line number Diff line number Diff line
@@ -384,7 +384,9 @@ struct link_resource { 


struct link_config {

	struct dc_link_settings dp_link_settings;

	struct dc_tunnel_settings dp_tunnel_settings;

};



union pipe_update_flags {

	struct {

		uint32_t enable : 1;

drivers/gpu/drm/amd/display/dc/inc/link.h

+3 −0
Original line number Diff line number Diff line
@@ -207,6 +207,9 @@ struct link_service { 
	bool (*dp_decide_link_settings)(

		struct dc_stream_state *stream,

		struct dc_link_settings *link_setting);

	void (*dp_decide_tunnel_settings)(

		struct dc_stream_state *stream,

		struct dc_tunnel_settings *dp_tunnel_setting);

	enum dp_link_encoding (*mst_decide_link_encoding_format)(

			const struct dc_link *link);

	bool (*edp_decide_link_settings)(struct dc_link *link,