Merge tag 'drm-misc-next-2025-07-03' of... (17d081ef) · Commits · git / linux-net

Documentation/devicetree/bindings/display/panel/himax,hx83112b.yaml

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+73 −0

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		# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/panel/himax,hx83112b.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Himax HX83112B-based DSI display panels

		maintainers:
		- Luca Weiss <luca@lucaweiss.eu>

		description:
		The Himax HX83112B is a generic DSI Panel IC used to control
		LCD panels.

		allOf:
		- $ref: panel-common.yaml#

		properties:
		compatible:
		contains:
		const: djn,98-03057-6598b-i

		reg:
		maxItems: 1

		iovcc-supply:
		description: I/O voltage rail

		vsn-supply:
		description: Positive source voltage rail

		vsp-supply:
		description: Negative source voltage rail

		required:
		- compatible
		- reg
		- reset-gpios
		- iovcc-supply
		- vsn-supply
		- vsp-supply
		- port

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/gpio/gpio.h>

		dsi {
		#address-cells = <1>;
		#size-cells = <0>;

		panel@0 {
		compatible = "djn,98-03057-6598b-i";
		reg = <0>;

		reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;

		iovcc-supply = <&pm8953_l6>;
		vsn-supply = <&pmi632_lcdb_ncp>;
		vsp-supply = <&pmi632_lcdb_ldo>;

		port {
		panel_in_0: endpoint {
		remote-endpoint = <&dsi0_out>;
		};
		};
		};
		};

		...

Documentation/devicetree/bindings/display/panel/raydium,rm67200.yaml

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		@@ -42,7 +42,6 @@ required:
		- compatible
		- port
		- reg
		- reset-gpios

		additionalProperties: false

Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

+44 −12

Original line number	Diff line number	Diff line
		@@ -64,10 +64,10 @@ properties:
		- description: Pixel clock for video port 0.
		- description: Pixel clock for video port 1.
		- description: Pixel clock for video port 2.
		- description: Pixel clock for video port 3.
		- description: Peripheral(vop grf/dsi) clock.
		- description: Alternative pixel clock provided by HDMI0 PHY PLL.
		- description: Alternative pixel clock provided by HDMI1 PHY PLL.
		- {}
		- {}
		- {}
		- {}

		clock-names:
		minItems: 5
		@@ -77,10 +77,10 @@ properties:
		- const: dclk_vp0
		- const: dclk_vp1
		- const: dclk_vp2
		- const: dclk_vp3
		- const: pclk_vop
		- const: pll_hdmiphy0
		- const: pll_hdmiphy1
		- {}
		- {}
		- {}
		- {}

		rockchip,grf:
		$ref: /schemas/types.yaml#/definitions/phandle
		@@ -175,10 +175,24 @@ allOf:
		then:
		properties:
		clocks:
		maxItems: 5
		minItems: 5
		items:
		- {}
		- {}
		- {}
		- {}
		- {}
		- description: Alternative pixel clock provided by HDMI PHY PLL.

		clock-names:
		maxItems: 5
		minItems: 5
		items:
		- {}
		- {}
		- {}
		- {}
		- {}
		- const: pll_hdmiphy0

		interrupts:
		minItems: 4
		@@ -208,11 +222,29 @@ allOf:
		properties:
		clocks:
		minItems: 7
		maxItems: 9
		items:
		- {}
		- {}
		- {}
		- {}
		- {}
		- description: Pixel clock for video port 3.
		- description: Peripheral(vop grf/dsi) clock.
		- description: Alternative pixel clock provided by HDMI0 PHY PLL.
		- description: Alternative pixel clock provided by HDMI1 PHY PLL.

		clock-names:
		minItems: 7
		maxItems: 9
		items:
		- {}
		- {}
		- {}
		- {}
		- {}
		- const: dclk_vp3
		- const: pclk_vop
		- const: pll_hdmiphy0
		- const: pll_hdmiphy1

		interrupts:
		maxItems: 1

Documentation/devicetree/bindings/display/ti/ti,am625-oldi.yaml

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+79 −0

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/ti/ti,am625-oldi.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Texas Instruments AM625 OLDI Transmitter

		maintainers:
		- Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
		- Aradhya Bhatia <aradhya.bhatia@linux.dev>

		description:
		The AM625 TI Keystone OpenLDI transmitter (OLDI TX) supports serialized RGB
		pixel data transmission between host and flat panel display over LVDS (Low
		Voltage Differential Sampling) interface. The OLDI TX consists of 7-to-1 data
		serializers, and 4-data and 1-clock LVDS outputs. It supports the LVDS output
		formats "jeida-18", "jeida-24" and "vesa-18", and can accept 24-bit RGB or
		padded and un-padded 18-bit RGB bus formats as input.

		properties:
		reg:
		maxItems: 1

		clocks:
		maxItems: 1
		description: serial clock input for the OLDI transmitters

		clock-names:
		const: serial

		ti,companion-oldi:
		$ref: /schemas/types.yaml#/definitions/phandle
		description:
		phandle to companion OLDI transmitter. This property is required for both
		the OLDI TXes if they are expected to work either in dual-lvds mode or in
		clone mode. This property should point to the other OLDI TX's phandle.

		ti,secondary-oldi:
		type: boolean
		description:
		Boolean property to mark the OLDI transmitter as the secondary one, when the
		OLDI hardware is expected to run as a companion HW, in cases of dual-lvds
		mode or clone mode. The primary OLDI hardware is responsible for all the
		hardware configuration.

		ti,oldi-io-ctrl:
		$ref: /schemas/types.yaml#/definitions/phandle
		description:
		phandle to syscon device node mapping OLDI IO_CTRL registers found in the
		control MMR region. These registers are required to toggle the I/O lane
		power, and control its electrical characteristics.

		ports:
		$ref: /schemas/graph.yaml#/properties/ports

		properties:
		port@0:
		$ref: /schemas/graph.yaml#/properties/port
		description: Parallel RGB input port

		port@1:
		$ref: /schemas/graph.yaml#/properties/port
		description: LVDS output port

		required:
		- port@0
		- port@1

		required:
		- reg
		- clocks
		- clock-names
		- ti,oldi-io-ctrl
		- ports

		additionalProperties: false

		...

Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml

+178 −21

Original line number	Diff line number	Diff line
		@@ -100,6 +100,24 @@ properties:
		For AM62A7 DSS, the port is tied off inside the SoC.
		For AM62L DSS, the DSS DPI output port node from video port 1
		or DSI Tx controller node connected to video port 1.
		properties:
		endpoint@0:
		$ref: /schemas/graph.yaml#/properties/endpoint
		description:
		For AM625 DSS, VP Connection to OLDI0.
		For AM65X DSS, OLDI output from the SoC.

		endpoint@1:
		$ref: /schemas/graph.yaml#/properties/endpoint
		description:
		For AM625 DSS, VP Connection to OLDI1.

		anyOf:
		- required:
		- endpoint
		- required:
		- endpoint@0
		- endpoint@1

		port@1:
		$ref: /schemas/graph.yaml#/properties/port
		@@ -121,6 +139,25 @@ properties:
		Input memory (from main memory to dispc) bandwidth limit in
		bytes per second

		oldi-transmitters:
		description:
		Child node under the DSS, to describe all the OLDI transmitters connected
		to the DSS videoports.
		type: object
		additionalProperties: false

		properties:
		"#address-cells":
		const: 1

		"#size-cells":
		const: 0

		patternProperties:
		'^oldi@[0-1]$':
		$ref: ti,am625-oldi.yaml#
		description: OLDI transmitters connected to the DSS VPs

		allOf:
		- if:
		properties:
		@@ -129,6 +166,7 @@ allOf:
		const: ti,am62a7-dss
		then:
		properties:
		oldi-transmitters: false
		ports:
		properties:
		port@0: false
		@@ -143,6 +181,22 @@ allOf:
		properties:
		port@1: false

		- if:
		properties:
		compatible:
		contains:
		enum:
		- ti,am62l-dss
		- ti,am65x-dss
		then:
		properties:
		oldi-transmitters: false
		ports:
		properties:
		port@0:
		properties:
		endpoint@1: false

		required:
		- compatible
		- reg
		@@ -190,3 +244,106 @@ examples:
		};
		};
		};

		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interrupt-controller/irq.h>
		#include <dt-bindings/soc/ti,sci_pm_domain.h>

		bus {
		#address-cells = <2>;
		#size-cells = <2>;
		dss1: dss@30200000 {
		compatible = "ti,am625-dss";
		reg = <0x00 0x30200000 0x00 0x1000>, /* common */
		<0x00 0x30202000 0x00 0x1000>, /* vidl1 */
		<0x00 0x30206000 0x00 0x1000>, /* vid */
		<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
		<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
		<0x00 0x3020a000 0x00 0x1000>, /* vp1 */
		<0x00 0x3020b000 0x00 0x1000>, /* vp2 */
		<0x00 0x30201000 0x00 0x1000>; /* common1 */
		reg-names = "common", "vidl1", "vid",
		"ovr1", "ovr2", "vp1", "vp2", "common1";
		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 186 6>,
		<&vp1_clock>,
		<&k3_clks 186 2>;
		clock-names = "fck", "vp1", "vp2";
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		oldi-transmitters {
		#address-cells = <1>;
		#size-cells = <0>;
		oldi0: oldi@0 {
		reg = <0>;
		clocks = <&k3_clks 186 0>;
		clock-names = "serial";
		ti,companion-oldi = <&oldi1>;
		ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		oldi0_in: endpoint {
		remote-endpoint = <&dpi0_out0>;
		};
		};
		port@1 {
		reg = <1>;
		oldi0_out: endpoint {
		remote-endpoint = <&panel_in0>;
		};
		};
		};
		};
		oldi1: oldi@1 {
		reg = <1>;
		clocks = <&k3_clks 186 0>;
		clock-names = "serial";
		ti,secondary-oldi;
		ti,companion-oldi = <&oldi0>;
		ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		oldi1_in: endpoint {
		remote-endpoint = <&dpi0_out1>;
		};
		};
		port@1 {
		reg = <1>;
		oldi1_out: endpoint {
		remote-endpoint = <&panel_in1>;
		};
		};
		};
		};
		};
		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;
		dpi0_out0: endpoint@0 {
		reg = <0>;
		remote-endpoint = <&oldi0_in>;
		};
		dpi0_out1: endpoint@1 {
		reg = <1>;
		remote-endpoint = <&oldi1_in>;
		};
		};
		port@1 {
		reg = <1>;
		dpi1_out: endpoint {
		remote-endpoint = <&hdmi_bridge>;
		};
		};
		};
		};
		};