Commit 17efc1ac authored by Oliver Upton's avatar Oliver Upton Committed by Will Deacon
Browse files

arm64: Expose AIDR_EL1 via sysfs 



The KVM PV ABI recently added a feature that allows the VM to discover
the set of physical CPU implementations, identified by a tuple of
{MIDR_EL1, REVIDR_EL1, AIDR_EL1}. Unlike other KVM PV features, the
expectation is that the VMM implements the hypercall instead of KVM as
it has the authoritative view of where the VM gets scheduled.

To do this the VMM needs to know the values of these registers on any
CPU in the system. While MIDR_EL1 and REVIDR_EL1 are already exposed,
AIDR_EL1 is not. Provide it in sysfs along with the other identification
registers.

Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
Reviewed-by: default avatarCornelia Huck <cohuck@redhat.com>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20250403231626.3181116-1-oliver.upton@linux.dev


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 35382a36

Documentation/ABI/testing/sysfs-devices-system-cpu

+1 −0
Original line number Diff line number Diff line
@@ -485,6 +485,7 @@ What: /sys/devices/system/cpu/cpuX/regs/ 
		/sys/devices/system/cpu/cpuX/regs/identification/

		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/aidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1

Date:		June 2016

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Documentation/arch/arm64/cpu-feature-registers.rst

+7 −6
Original line number Diff line number Diff line
@@ -72,14 +72,15 @@ there are some issues with their usage. 
    process could be migrated to another CPU by the time it uses the

    register value, unless the CPU affinity is set. Hence, there is no

    guarantee that the value reflects the processor that it is

    currently executing on. The REVIDR is not exposed due to this

    constraint, as REVIDR makes sense only in conjunction with the

    MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs

    at::

    currently executing on. REVIDR and AIDR are not exposed due to this

    constraint, as these registers only make sense in conjunction with

    the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed

    via sysfs at::



	/sys/devices/system/cpu/cpu$ID/regs/identification/

	                                              \- midr

	                                              \- revidr

	                                              \- midr_el1

	                                              \- revidr_el1

	                                              \- aidr_el1



3. Implementation

--------------------

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct cpuinfo_arm64 { 
	u64		reg_dczid;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_aidr;

	u64		reg_gmid;

	u64		reg_smidr;

	u64		reg_mpamidr;

arch/arm64/kernel/cpuinfo.c

+3 −0
Original line number Diff line number Diff line
@@ -328,11 +328,13 @@ static const struct kobj_type cpuregs_kobj_type = { 


CPUREGS_ATTR_RO(midr_el1, midr);

CPUREGS_ATTR_RO(revidr_el1, revidr);

CPUREGS_ATTR_RO(aidr_el1, aidr);

CPUREGS_ATTR_RO(smidr_el1, smidr);



static struct attribute *cpuregs_id_attrs[] = {

	&cpuregs_attr_midr_el1.attr,

	&cpuregs_attr_revidr_el1.attr,

	&cpuregs_attr_aidr_el1.attr,

	NULL

};
@@ -469,6 +471,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_dczid = read_cpuid(DCZID_EL0);

	info->reg_midr = read_cpuid_id();

	info->reg_revidr = read_cpuid(REVIDR_EL1);

	info->reg_aidr = read_cpuid(AIDR_EL1);



	info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);

	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);