Commit 1800c660 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/layerscape' 

- Add suspend/resume support for Layerscape LS1043a, including
  software-managed PME_Turn_Off and transitions between L0, L2/L3_Ready
  Link states (Frank Li)

* pci/controller/layerscape:
  PCI: layerscape: Add suspend/resume for ls1043a
  PCI: layerscape(ep): Rename pf_* as pf_lut_*
  PCI: layerscape: Add suspend/resume for ls1021a
  PCI: layerscape: Add function pointer for exit_from_l2()
parents 921e097e 27b3bcbf

drivers/pci/controller/dwc/pci-layerscape-ep.c

+8 −8
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ struct ls_pcie_ep { 
	bool				big_endian;

};



static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)

static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset)

{

	struct dw_pcie *pci = pcie->pci;
@@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) 
		return ioread32(pci->dbi_base + offset);

}



static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)

static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)

{

	struct dw_pcie *pci = pcie->pci;
@@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
	u32 val, cfg;

	u8 offset;



	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);

	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);

	val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);

	ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);



	if (!val)

		return IRQ_NONE;
@@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);

		dw_pcie_dbi_ro_wr_dis(pci);



		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);

		cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);

		cfg |= PEX_PF0_CFG_READY;

		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);

		ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg);

		dw_pcie_ep_linkup(&pci->ep);



		dev_dbg(pci->dev, "Link up\n");
@@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, 
	}



	/* Enable interrupts */

	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER);

	val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER);

	val |=  PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |

		PEX_PF0_PME_MES_IER_LUDIE;

	ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);

	ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);



	return 0;

}

drivers/pci/controller/dwc/pci-layerscape.c

+168 −23
Original line number Diff line number Diff line
@@ -35,21 +35,41 @@ 
#define PF_MCR_PTOMR		BIT(0)

#define PF_MCR_EXL2S		BIT(1)



/* LS1021A PEXn PM Write Control Register */

#define SCFG_PEXPMWRCR(idx)	(0x5c + (idx) * 0x64)

#define PMXMTTURNOFF		BIT(31)

#define SCFG_PEXSFTRSTCR	0x190

#define PEXSR(idx)		BIT(idx)



/* LS1043A PEX PME control register */

#define SCFG_PEXPMECR		0x144

#define PEXPME(idx)		BIT(31 - (idx) * 4)



/* LS1043A PEX LUT debug register */

#define LS_PCIE_LDBG	0x7fc

#define LDBG_SR		BIT(30)

#define LDBG_WE		BIT(31)



#define PCIE_IATU_NUM		6



struct ls_pcie_drvdata {

	const u32 pf_off;

	const u32 pf_lut_off;

	const struct dw_pcie_host_ops *ops;

	int (*exit_from_l2)(struct dw_pcie_rp *pp);

	bool scfg_support;

	bool pm_support;

};



struct ls_pcie {

	struct dw_pcie *pci;

	const struct ls_pcie_drvdata *drvdata;

	void __iomem *pf_base;

	void __iomem *pf_lut_base;

	struct regmap *scfg;

	int index;

	bool big_endian;

};



#define ls_pcie_pf_readl_addr(addr)	ls_pcie_pf_readl(pcie, addr)

#define ls_pcie_pf_lut_readl_addr(addr)	ls_pcie_pf_lut_readl(pcie, addr)

#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)



static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
@@ -90,20 +110,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) 
	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);

}



static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)

static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)

{

	if (pcie->big_endian)

		return ioread32be(pcie->pf_base + off);

		return ioread32be(pcie->pf_lut_base + off);



	return ioread32(pcie->pf_base + off);

	return ioread32(pcie->pf_lut_base + off);

}



static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)

static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)

{

	if (pcie->big_endian)

		iowrite32be(val, pcie->pf_base + off);

		iowrite32be(val, pcie->pf_lut_base + off);

	else

		iowrite32(val, pcie->pf_base + off);

		iowrite32(val, pcie->pf_lut_base + off);

}



static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
@@ -113,11 +133,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) 
	u32 val;

	int ret;



	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_PTOMR;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);



	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_PTOMR),

				 PCIE_PME_TO_L2_TIMEOUT_US/10,

				 PCIE_PME_TO_L2_TIMEOUT_US);
@@ -125,7 +145,7 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) 
		dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");

}



static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)

static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -136,20 +156,22 @@ static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) 
	 * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link

	 * to exit L2 state.

	 */

	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_EXL2S;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);



	/*

	 * L2 exit timeout of 10ms is not defined in the specifications,

	 * it was chosen based on empirical observations.

	 */

	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_EXL2S),

				 1000,

				 10000);

	if (ret)

		dev_err(pcie->pci->dev, "L2 exit timeout\n");



	return ret;

}



static int ls_pcie_host_init(struct dw_pcie_rp *pp)
@@ -168,25 +190,130 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) 
	return 0;

}



static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask)

{

	/* Send PME_Turn_Off message */

	regmap_write_bits(scfg, reg, mask, mask);



	/*

	 * There is no specific register to check for PME_To_Ack from endpoint.

	 * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US.

	 */

	mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);



	/*

	 * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit

	 * to complete the PME_Turn_Off handshake.

	 */

	regmap_write_bits(scfg, reg, mask, 0);

}



static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);



	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);

}



static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask)

{

	/* Reset the PEX wrapper to bring the link out of L2 */

	regmap_write_bits(scfg, reg, mask, mask);

	regmap_write_bits(scfg, reg, mask, 0);



	return 0;

}



static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);



	return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));

}



static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);



	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));

}



static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);

	u32 val;



	/*

	 * Reset the PEX wrapper to bring the link out of L2.

	 * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and

	 *	    clearing the soft reset on the PEX module.

	 * LDBG_SR: When SR is set to 1, the PEX module enters soft reset.

	 */

	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);

	val |= LDBG_WE;

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);



	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);

	val |= LDBG_SR;

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);



	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);

	val &= ~LDBG_SR;

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);



	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);

	val &= ~LDBG_WE;

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);



	return 0;

}



static const struct dw_pcie_host_ops ls_pcie_host_ops = {

	.init = ls_pcie_host_init,

	.pme_turn_off = ls_pcie_send_turnoff_msg,

};



static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {

	.init = ls_pcie_host_init,

	.pme_turn_off = ls1021a_pcie_send_turnoff_msg,

};



static const struct ls_pcie_drvdata ls1021a_drvdata = {

	.pm_support = false,

	.pm_support = true,

	.scfg_support = true,

	.ops = &ls1021a_pcie_host_ops,

	.exit_from_l2 = ls1021a_pcie_exit_from_l2,

};



static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = {

	.init = ls_pcie_host_init,

	.pme_turn_off = ls1043a_pcie_send_turnoff_msg,

};



static const struct ls_pcie_drvdata ls1043a_drvdata = {

	.pf_lut_off = 0x10000,

	.pm_support = true,

	.scfg_support = true,

	.ops = &ls1043a_pcie_host_ops,

	.exit_from_l2 = ls1043a_pcie_exit_from_l2,

};



static const struct ls_pcie_drvdata layerscape_drvdata = {

	.pf_off = 0xc0000,

	.pf_lut_off = 0xc0000,

	.pm_support = true,

	.ops = &ls_pcie_host_ops,

	.exit_from_l2 = ls_pcie_exit_from_l2,

};



static const struct of_device_id ls_pcie_of_match[] = {

	{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },

	{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata },

	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },

	{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
@@ -201,6 +328,8 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	struct dw_pcie *pci;

	struct ls_pcie *pcie;

	struct resource *dbi_base;

	u32 index[2];

	int ret;



	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);

	if (!pcie)
@@ -213,9 +342,8 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	pcie->drvdata = of_device_get_match_data(dev);



	pci->dev = dev;

	pci->pp.ops = &ls_pcie_host_ops;



	pcie->pci = pci;

	pci->pp.ops = pcie->drvdata->ops;



	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");

	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
@@ -224,7 +352,21 @@ static int ls_pcie_probe(struct platform_device *pdev) 


	pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");



	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;

	pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;



	if (pcie->drvdata->scfg_support) {

		pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");

		if (IS_ERR(pcie->scfg)) {

			dev_err(dev, "No syscfg phandle specified\n");

			return PTR_ERR(pcie->scfg);

		}



		ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);

		if (ret)

			return ret;



		pcie->index = index[1];

	}



	if (!ls_pcie_is_bridge(pcie))

		return -ENODEV;
@@ -247,11 +389,14 @@ static int ls_pcie_suspend_noirq(struct device *dev) 
static int ls_pcie_resume_noirq(struct device *dev)

{

	struct ls_pcie *pcie = dev_get_drvdata(dev);

	int ret;



	if (!pcie->drvdata->pm_support)

		return 0;



	ls_pcie_exit_from_l2(&pcie->pci->pp);

	ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp);

	if (ret)

		return ret;



	return dw_pcie_resume_noirq(pcie->pci);

}