Commit 18db1b6d authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Revert "Loongarch: Support loongarch avec" 



This reverts commit 760d7e71.

This results in build failures and has other issues according to Tianyang.

Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Tianyang Zhang <zhangtianyang@loongson.cn>
Closes: https://lore.kernel.org/oe-kbuild-all/202406240451.ygBFNyJ3-lkp@intel.com/
parent f2605e17

arch/loongarch/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -83,7 +83,6 @@ config LOONGARCH 
	select GENERIC_ENTRY

	select GENERIC_GETTIMEOFDAY

	select GENERIC_IOREMAP if !ARCH_IOREMAP

	select GENERIC_IRQ_MATRIX_ALLOCATOR

	select GENERIC_IRQ_MULTI_HANDLER

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

arch/loongarch/include/asm/cpu-features.h

+0 −1
Original line number Diff line number Diff line
@@ -65,6 +65,5 @@ 
#define cpu_has_guestid		cpu_opt(LOONGARCH_CPU_GUESTID)

#define cpu_has_hypervisor	cpu_opt(LOONGARCH_CPU_HYPERVISOR)

#define cpu_has_ptw		cpu_opt(LOONGARCH_CPU_PTW)

#define cpu_has_avecint		cpu_opt(LOONGARCH_CPU_AVECINT)



#endif /* __ASM_CPU_FEATURES_H */

arch/loongarch/include/asm/cpu.h

+0 −2
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ enum cpu_type_enum { 
#define CPU_FEATURE_GUESTID		24	/* CPU has GuestID feature */

#define CPU_FEATURE_HYPERVISOR		25	/* CPU has hypervisor (running in VM) */

#define CPU_FEATURE_PTW			26	/* CPU has hardware page table walker */

#define CPU_FEATURE_AVECINT		27	/* CPU has avec interrupt */



#define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)

#define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)
@@ -128,6 +127,5 @@ enum cpu_type_enum { 
#define LOONGARCH_CPU_GUESTID		BIT_ULL(CPU_FEATURE_GUESTID)

#define LOONGARCH_CPU_HYPERVISOR	BIT_ULL(CPU_FEATURE_HYPERVISOR)

#define LOONGARCH_CPU_PTW		BIT_ULL(CPU_FEATURE_PTW)

#define LOONGARCH_CPU_AVECINT		BIT_ULL(CPU_FEATURE_AVECINT)



#endif /* _ASM_CPU_H */

arch/loongarch/include/asm/hw_irq.h

+0 −10
Original line number Diff line number Diff line
@@ -9,16 +9,6 @@ 


extern atomic_t irq_err_count;



/*

 * 256 vectors Map:

 *

 * 0 - 15: mapping legacy IPs, e.g. IP0-12.

 * 16 - 255: mapping a vector for external IRQ.

 *

 */

#define NR_VECTORS		256

#define IRQ_MATRIX_BITS		NR_VECTORS

#define NR_LEGACY_VECTORS	16

/*

 * interrupt-retrigger: NOP for now. This may not be appropriate for all

 * machines, we'll see ...

arch/loongarch/include/asm/irq.h

+1 −11
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ extern struct acpi_vector_group msi_group[MAX_IO_PICS]; 
#define LOONGSON_LPC_LAST_IRQ		(LOONGSON_LPC_IRQ_BASE + 15)



#define LOONGSON_CPU_IRQ_BASE		16

#define LOONGSON_CPU_LAST_IRQ		(LOONGSON_CPU_IRQ_BASE + 15)

#define LOONGSON_CPU_LAST_IRQ		(LOONGSON_CPU_IRQ_BASE + 14)



#define LOONGSON_PCH_IRQ_BASE		64

#define LOONGSON_PCH_ACPI_IRQ		(LOONGSON_PCH_IRQ_BASE + 47)
@@ -101,16 +101,6 @@ int pch_msi_acpi_init(struct irq_domain *parent, 
					struct acpi_madt_msi_pic *acpi_pchmsi);

int pch_pic_acpi_init(struct irq_domain *parent,

					struct acpi_madt_bio_pic *acpi_pchpic);



#ifdef CONFIG_ACPI

int __init pch_msi_acpi_init_v2(struct irq_domain *parent,

		struct acpi_madt_msi_pic *pch_msi_entry);

int __init loongarch_avec_acpi_init(struct irq_domain *parent);

void complete_irq_moving(void);

void loongarch_avec_offline_cpu(unsigned int cpu);

void loongarch_avec_online_cpu(unsigned int cpu);

#endif



int find_pch_pic(u32 gsi);

struct fwnode_handle *get_pch_msi_handle(int pci_segment);