Commit 18fc0f1d authored by Varun Gupta's avatar Varun Gupta Committed by Tejas Upadhyay
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drm/xe/xe3p_lpg: Add Wa_16029437861 



Wa_16029437861 requires disabling COAMA atomics by setting bit 22
(SQ_DISABLE_COAMA) of L3SQCREG2 (0xb104) for Xe3p_LPG graphics
version 35.10 stepping A0..B0. This bit is already set by the existing
Wa_14026144927 entry, so add the new WA ID to the same implementation.

Signed-off-by: default avatarVarun Gupta <varun.gupta@intel.com>
Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patch.msgid.link/20260317040447.1792687-1-varun.gupta@intel.com


Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
parent c56af8fe

drivers/gpu/drm/xe/xe_wa.c

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,

			     DIS_ATS_WRONLY_PG))

	},

	{ XE_RTP_NAME("14026144927"),

	{ XE_RTP_NAME("14026144927, 16029437861"),

	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),

	  XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |

			     L3_SQ_DISABLE_COAMA))