Unverified Commit 19024c99 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Stephen Boyd
Browse files

clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks 



All the MFGPLL require MFG_EB to be on for any operation on them, and
they only tick when MFG_EB is on as well, therefore making this a
parent-child relationship.

This dependency wasn't clear during the initial upstreaming of these
clock controllers, as it only made itself known when I could observe
the effects of the clock by bringing up a different piece of hardware.

Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it
when initialising the pll to then translate it into the actual
CLK_OPS_PARENT_ENABLE flag.

Then add the mfg_eb parent to the mfgpll clocks, and set the new
PLL_PARENT_EN flag.

Fixes: 03dc02f8 ("clk: mediatek: Add MT8196 mfg clock support")
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 483f364b

drivers/clk/mediatek/clk-mt8196-mfg.c

+7 −6
Original line number Diff line number Diff line
@@ -58,24 +58,25 @@ 
		.pcw_shift = _pcw_shift,			\

		.pcwbits = _pcwbits,				\

		.pcwibits = MT8196_INTEGER_BITS,		\

		.parent_name = "mfg_eb",			\

	}



static const struct mtk_pll_data mfg_ao_plls[] = {

	PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,

	    BIT(0), MFGPLL_CON1, 24, 0, 0, 0,

	PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0,

	    PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,

	    MFGPLL_CON1, 0, 22),

};



static const struct mtk_pll_data mfgsc0_ao_plls[] = {

	PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,

	    MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,

	    MFGPLL_SC0_CON1, 0, 22),

	    MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,

	    0, 0, 0, MFGPLL_SC0_CON1, 0, 22),

};



static const struct mtk_pll_data mfgsc1_ao_plls[] = {

	PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,

	    MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,

	    MFGPLL_SC1_CON1, 0, 22),

	    MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,

	    0, 0, 0, MFGPLL_SC1_CON1, 0, 22),

};



static const struct of_device_id of_match_clk_mt8196_mfg[] = {

drivers/clk/mediatek/clk-pll.c

+3 −0
Original line number Diff line number Diff line
@@ -359,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, 


	init.name = data->name;

	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;

	if (data->flags & PLL_PARENT_EN)

		init.flags |= CLK_OPS_PARENT_ENABLE;



	init.ops = pll_ops;

	if (data->parent_name)

		init.parent_names = &data->parent_name;

drivers/clk/mediatek/clk-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ struct mtk_pll_div_table { 


#define HAVE_RST_BAR	BIT(0)

#define PLL_AO		BIT(1)

#define PLL_PARENT_EN	BIT(2)

#define POSTDIV_MASK	GENMASK(2, 0)



struct mtk_pll_data {