Commit 19281571 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom: qmp-usb: split USB-C PHY driver 



In preparation to adding Type-C handling for MSM8998, QCM2290 and SM6115
platforms, create new QMP USB-C PHY driver by splitting mentioned
platforms to a separate file. In future it will also be extended with
support for the DisplayPort handling. It will also be reused later for
such platforms as SDM660, SM6125, SM6150.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240113-pmi632-typec-v2-10-182d9aa0a5b3@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c1214b57

drivers/phy/qualcomm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o 
obj-$(CONFIG_PHY_QCOM_M31_USB)		+= phy-qcom-m31.o

obj-$(CONFIG_PHY_QCOM_PCIE2)		+= phy-qcom-pcie2.o



obj-$(CONFIG_PHY_QCOM_QMP_COMBO)	+= phy-qcom-qmp-combo.o

obj-$(CONFIG_PHY_QCOM_QMP_COMBO)	+= phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o

obj-$(CONFIG_PHY_QCOM_QMP_PCIE)		+= phy-qcom-qmp-pcie.o

obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996)	+= phy-qcom-qmp-pcie-msm8996.o

obj-$(CONFIG_PHY_QCOM_QMP_UFS)		+= phy-qcom-qmp-ufs.o

drivers/phy/qualcomm/phy-qcom-qmp-usb.c

+0 −266
Original line number Diff line number Diff line
@@ -121,15 +121,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_PCS_MISC_CLAMP_ENABLE]	= QPHY_V3_PCS_MISC_CLAMP_ENABLE,

};



static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V3_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V3_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]		= QPHY_V3_PCS_PCS_STATUS,

	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,

	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V3_PCS_POWER_DOWN_CONTROL,

};



static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V4_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V4_PCS_START_CONTROL,
@@ -514,115 +505,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),

};



static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),

};



static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),

};



static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),

};



static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

};



static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
@@ -1089,99 +971,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),

};



static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
@@ -1571,16 +1360,6 @@ static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { 
	.rx		= 0x400,

};



static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = {

	.serdes		= 0x0,

	.pcs		= 0xc00,

	.pcs_misc	= 0xa00,

	.tx		= 0x200,

	.rx		= 0x400,

	.tx2		= 0x600,

	.rx2		= 0x800,

};



static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {

	.serdes		= 0,

	.pcs		= 0x0800,
@@ -1727,24 +1506,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 
	.has_pwrdn_delay	= true,

};



static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_usb_offsets_v3_qcm2290,



	.serdes_tbl             = msm8998_usb3_serdes_tbl,

	.serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),

	.tx_tbl                 = msm8998_usb3_tx_tbl,

	.tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),

	.rx_tbl                 = msm8998_usb3_rx_tbl,

	.rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),

	.pcs_tbl                = msm8998_usb3_pcs_tbl,

	.pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),

	.vreg_list              = qmp_phy_vreg_l,

	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),

	.regs                   = qmp_v3_usb3phy_regs_layout,

};



static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {

	.lanes			= 1,
@@ -1882,24 +1643,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 
	.has_pwrdn_delay	= true,

};



static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_usb_offsets_v3_qcm2290,



	.serdes_tbl		= qcm2290_usb3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qcm2290_usb3_serdes_tbl),

	.tx_tbl			= qcm2290_usb3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_tx_tbl),

	.rx_tbl			= qcm2290_usb3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_rx_tbl),

	.pcs_tbl		= qcm2290_usb3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(qcm2290_usb3_pcs_tbl),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qmp_v3_usb3phy_regs_layout_qcm2290,

};



static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {

	.lanes			= 1,
@@ -2573,12 +2316,6 @@ static const struct of_device_id qmp_usb_of_match_table[] = { 
	}, {

		.compatible = "qcom,msm8996-qmp-usb3-phy",

		.data = &msm8996_usb3phy_cfg,

	}, {

		.compatible = "qcom,msm8998-qmp-usb3-phy",

		.data = &msm8998_usb3phy_cfg,

	}, {

		.compatible = "qcom,qcm2290-qmp-usb3-phy",

		.data = &qcm2290_usb3phy_cfg,

	}, {

		.compatible = "qcom,sa8775p-qmp-usb3-uni-phy",

		.data = &sa8775p_usb3_uniphy_cfg,
@@ -2597,9 +2334,6 @@ static const struct of_device_id qmp_usb_of_match_table[] = { 
	}, {

		.compatible = "qcom,sdx75-qmp-usb3-uni-phy",

		.data = &sdx75_usb3_uniphy_cfg,

	}, {

		.compatible = "qcom,sm6115-qmp-usb3-phy",

		.data = &qcm2290_usb3phy_cfg,

	}, {

		.compatible = "qcom,sm8150-qmp-usb3-uni-phy",

		.data = &sm8150_usb3_uniphy_cfg,

drivers/phy/qualcomm/phy-qcom-qmp-usbc.c

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+1078 −0

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