Commit 193650c7 authored by Brian Masney's avatar Brian Masney
Browse files

clk: zynqmp: pll: convert from round_rate() to determine_rate() 



The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: default avatarBrian Masney <bmasney@redhat.com>
parent 5352b650

drivers/clk/zynqmp/pll.c

+12 −12
Original line number Diff line number Diff line
@@ -98,29 +98,29 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) 
 *

 * Return: Frequency closest to @rate the hardware can generate

 */

static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				  unsigned long *prate)

static int zynqmp_pll_determine_rate(struct clk_hw *hw,

				     struct clk_rate_request *req)

{

	u32 fbdiv;

	u32 mult, div;



	/* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */

	if (rate > PS_PLL_VCO_MAX) {

		div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);

		rate = rate / div;

	if (req->rate > PS_PLL_VCO_MAX) {

		div = DIV_ROUND_UP(req->rate, PS_PLL_VCO_MAX);

		req->rate = req->rate / div;

	}

	if (rate < PS_PLL_VCO_MIN) {

		mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);

		rate = rate * mult;

	if (req->rate < PS_PLL_VCO_MIN) {

		mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, req->rate);

		req->rate = req->rate * mult;

	}



	fbdiv = DIV_ROUND_CLOSEST(rate, *prate);

	fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate);

	if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {

		fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);

		rate = *prate * fbdiv;

		req->rate = req->best_parent_rate * fbdiv;

	}



	return rate;

	return 0;

}



/**
@@ -294,7 +294,7 @@ static const struct clk_ops zynqmp_pll_ops = { 
	.enable = zynqmp_pll_enable,

	.disable = zynqmp_pll_disable,

	.is_enabled = zynqmp_pll_is_enabled,

	.round_rate = zynqmp_pll_round_rate,

	.determine_rate = zynqmp_pll_determine_rate,

	.recalc_rate = zynqmp_pll_recalc_rate,

	.set_rate = zynqmp_pll_set_rate,

};