Commit 19726428 authored by Victor Lu's avatar Victor Lu Committed by Alex Deucher
Browse files

drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2) 



W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.

v2: rebase

Signed-off-by: default avatarVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 85150626

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

+17 −21
Original line number Diff line number Diff line
@@ -306,8 +306,7 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 
	/* Activate doorbell logic before triggering WPTR poll. */

	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL),

				data);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);



	if (wptr) {

		/* Don't read wptr with get_user because the user
@@ -336,27 +335,24 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 
		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);

		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;



		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,

			lower_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,

			upper_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,

			lower_32_bits((uintptr_t)wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regCP_HQD_PQ_WPTR_POLL_ADDR_HI),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,

			upper_32_bits((uintptr_t)wptr));

		WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1),

		       (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,

			       queue_id));

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,

			(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));

	}



	/* Start the EOP fetcher */

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR),

	       REG_SET_FIELD(m->cp_hqd_eop_rptr,

			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,

	       REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));



	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);



	kgd_gfx_v9_release_queue(adev, inst);
@@ -494,15 +490,15 @@ static uint32_t kgd_gfx_v9_4_3_set_address_watch( 
			VALID,

			1);



	WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

	WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regTCP_WATCH0_ADDR_H) +

			(watch_id * TCP_WATCH_STRIDE)),

			watch_address_high);

			watch_address_high, inst);



	WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

	WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regTCP_WATCH0_ADDR_L) +

			(watch_id * TCP_WATCH_STRIDE)),

			watch_address_low);

			watch_address_low, inst);



	return watch_address_cntl;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+19 −21
Original line number Diff line number Diff line
@@ -91,8 +91,8 @@ void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmi 
{

	kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);



	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);

	/* APE1 no longer exists on GFX9 */



	kgd_gfx_v9_unlock_srbm(adev, inst);
@@ -245,8 +245,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, 
	/* Activate doorbell logic before triggering WPTR poll. */

	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL),

					data);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);



	if (wptr) {

		/* Don't read wptr with get_user because the user
@@ -275,25 +274,24 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, 
		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);

		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;



		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,

			lower_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

			upper_32_bits(guessed_wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,

			lower_32_bits((uintptr_t)wptr));

		WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

			upper_32_bits((uintptr_t)wptr));

		WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

		WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,

			(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));

	}



	/* Start the EOP fetcher */

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR),

	       REG_SET_FIELD(m->cp_hqd_eop_rptr,

			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,

	       REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));



	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);



	kgd_gfx_v9_release_queue(adev, inst);
@@ -556,7 +554,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, 
		break;

	}



	WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type);

	WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);



	end_jiffies = (utimeout * HZ / 1000) + jiffies;

	while (true) {
@@ -908,8 +906,8 @@ void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev, 
					uint32_t inst)



{

	*wait_times = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			mmCP_IQ_WAIT_TIME2));

	*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),

			mmCP_IQ_WAIT_TIME2);

}



void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+1 −1
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ 


/* for GC only */

#define RREG32_RLC(reg) \

	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)

	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)



#define WREG32_RLC_NO_KIQ(reg, value, hwip) \

	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)